TMD3721 datasheet(36/89 Pages) AMSCO

36 / 89 page

Datasheet, Public

Page 35

[v3-00] 2023-May-26

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TMD3721 − Register Overview

PCFG2 Register (Address 0x90)

Figure 42:

PCFG2 Register

REVID Register (Address 0x91)

Figure 43:

REVID Register

ID Register (Address 0x92)

Figure 44:

ID Register

Addr: 0x90

PCFG2

Bit

Bit Name

Default

Access

Bit Description

7:0

PPULSE_LENL

0x20

These bits are the 8 least significant bits of the 10-bit

Pulse Length control setting. The upper 2 bits are in

the PCFG1 register. See the PCFG1 register for details.

Pulse Length needs to be greater than 16μs.

Value

Pulse Length

14 (0000001110)

16μs

15 (0000001111)

17μs

Pulse Length = (PPULSE_LEN + 2)μs

1023 (1111111111)

1025μs

Addr: 0x91

REVID

Bit

Bit Name

Default

Access

Bit Description

7:5

Reserved

000

Reserved

4:3

FUNC_ID

Device function identification

2:0

REV_ID

001

Device revision number

Addr: 0x92

Bit

Bit Name

Default

Access

Bit Description

7:0

0x82

Device identification

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