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TMD3721 数据表(PDF) 21 Page - ams AG |
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TMD3721 数据表(HTML) 21 Page - ams AG |
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21 / 89 page  Page 20 Datasheet, Public Document Feedback [v3-00] 2023-May-26 TMD3721 − Detailed Description Figure 20: I²C Timing Characteristics I²C Timing Diagram Figure 21: I²C Timing Diagram Symbol Parameter Min Type Max Unit fSCL I²C clock frequency 0400 kHz tBUF Bus free time between start and stop condition 1.3 μs tHD;STA Hold time after (repeated) start condition. After this period, the first clock is generated 0.6 tSU;STA Repeated start condition setup time 0.6 tSU;STO Stop condition setup time 0.6 tLOW SCL clock low period 1.3 tHIGH SCL clock high period 0.6 tHD;DAT Data hold time 0 ns tSU;DAT Data setup time 100 tF Clock/data fall time 300 tR Clock/data rise time 300 |
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