GS66508B

Bottom-side cooled 650 V E-mode GaN transistor

Datasheet

Rev 200402

© 2009-2020 GaN Systems Inc.

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Application Information

Gate Drive

The recommended gate drive voltage range, VGS, is 0 V to + 6 V for optimal RDS(on) performance. Also, the

repetitive gate to source voltage, maximum rating, VGS(AC), is +7 V to -10 V. The gate can survive non-repetitive

transients up to +10 V and – 20 V for pulses up to 1 µs. These specifications allow designers to easily use 6.0 V

or 6.5 V gate drive settings. At 6 V gate drive voltage, the enhancement mode high electron mobility transistor

(E-HEMT) is fully enhanced and reaches its optimal efficiency point. A 5 V gate drive can be used but may result

in lower operating efficiency. Inherently, GaN Systems E-HEMT do not require negative gate bias to turn off.

Negative gate bias, typically VGS = -3 V, ensures safe operation against the voltage spike on the gate, however it

may increase reverse conduction losses if not driven properly. For more details, please refer to the gate driver

application note "GN001 How to Drive GaN Enhancement Mode Power Switching Transistors” at

www.gansystems.com

Similar to a silicon MOSFET, an external gate resistor can be used to control the switching speed and slew rate.

Adjusting the resistor to achieve the desired slew rate may be needed. Lower turn-off gate resistance, RG(OFF) is

recommended for better immunity to cross conduction. Please see the gate driver application note (GN001) for

more details.

A standard MOSFET driver can be used as long as it supports 6 V for gate drive and the UVLO is suitable for 6 V

operation. Gate drivers with low impedance and high peak current are recommended for fast switching speed.

GaN Systems E-HEMTs have significantly lower QG when compared to equally sized RDS(on) MOSFETs, so high

speed can be reached with smaller and lower cost gate drivers.

Some non-isolated half bridge MOSFET drivers are not compatible with 6 V gate drive due to their high under-

voltage lockout threshold. Also, a simple bootstrap method for high side gate drive may not be able to provide

tight tolerance on the gate voltage. Therefore, special care should be taken when you select and use the half

bridge drivers. Please see the gate driver application note (GN001) for more details.

Parallel Operation

Design wide tracks or polygons on the PCB to distribute the gate drive signals to multiple devices. Keep the

drive loop length to each device as short and equal length as possible.

GaN enhancement mode HEMTs have a positive temperature coefficient on-state resistance which helps to

balance the current. However, special care should be taken in the driver circuit and PCB layout since the device

switches at very fast speed. It is recommended to have a symmetric PCB layout and equal gate drive loop length

(star connection if possible) on all parallel devices to ensure balanced dynamic current sharing. Adding a small

gate resistor (1-2 Ω) on each gate is strongly recommended to minimize the gate parasitic oscillation.