GWIXC1100BCT datasheet(125/134 Pages) INTEL

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

Datasheet

March 2005

Document Number: 252479, Revision: 005

125

5.5.2.7.1

EX_IOWAIT_N

The EX_IOWAIT_N signal is available to be shared by devices attached to Chip Selects 0 through

7 and is used as required by slow devices.

If the external device asserts EX_IOWAIT_N during the strobe phase of a read transfer, the

controller will hold in that phase until the EX_IOWAIT_N goes false. At that time, the controller

will immediately transition to the hold phase regardless of the setting of the programming

parameter (T3) for the strobe phase.

The EX_IOWAIT_N signal only affects the interface during the strobe phase of a read transfer. If

Chip Selects 4 through 7 are configured in HPI mode of operation, each chip select will have a

corresponding HRDY signal called EX_RDY. The polarity of the ready signal is programmable.

Chip Select 4 corresponds to EX_RDY signal 0 and Chip Select 7 corresponds to EX_RDY signal

5.5.2.8

High-Speed, Serial Interfaces

Figure 41.

High-Speed, Serial Timings

A9594-01

hss_txclk/

hss_rxclk1

hss_(tx or rx)frame

(Positive edge)

hss_(tx or rx)frame

(Negative edge)

hss_ rxdata

(Positive edge)

As Inputs:

Valid Data

hss_ rxdata

(Negative edge)

hss_(tx or rx)frame

(Positive edge)

hss_(tx or rx)frame

(Negative edge)

hss_ txdata

(Positive edge)

hss_ txdata

(Negative edge)

As Outputs:

Valid Data

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