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GWIXC1100BCT 数据表(PDF) 127 Page - Intel Corporation |
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GWIXC1100BCT 数据表(HTML) 127 Page - Intel Corporation |
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127 / 134 page  Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet March 2005 Document Number: 252479, Revision: 005 127 5.5.2.9 JTAG Figure 42. Boundary-Scan General Timings Figure 43. Boundary-Scan Reset Timings Table 65. Boundary-Scan Interface Timings Values Symbol Parameter Conditions Min. Typ. Max. Units Notes Tbscl JTAG_TCK low time 50 ns 2 Tbsch JTAG_TCK high time 50 ns 2 Tbsis JTAG_TDI, JTAG_TMS setup time to rising edge of JTAG_TCK 10 ns Tbsih JTAG_TDI, JTAG_TMS hold time from rising edge of JTAG_TCK 10 ns Tbsoh JTAG_TDO hold time after falling edge of JTAG_TCK 1.5 ns 1 Tbsod JTAG_TDO clock to output from falling edge of JTAG_TCK 40 ns 1 Tbsr JTAG_TRST_N reset period 30 ns Tbsrs JTAG_TMS setup time to rising edge of JTAG_TRST_N 10 ns Tbsrh JTAG_TMS hold time from rising edge of JTAG_TRST_N 10 ns Notes: 1. Tests completed with a TBD pF load to ground on JTAG_TDO. 2. JTAG_TCK may be stopped indefinitely in either the low or high phase. B0416-01 Tbsel Tbsis Tbsih Tbsch JTG_TCK JTG_TMS, JTG_TDI JTG_TDO Tbsoh Tbsod A9597-01 Tbsr Tbsrs Tbsrh JTG_TRST_N JTG_TMS |
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