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MCP621 数据表(PDF) 21 Page - Microchip Technology

部件名 MCP621
功能描述  20 MHz, 200 μV Op Amps with mCal
PDF  68 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP621 数据表(HTML) 21 Page - Microchip Technology

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 2009-2021 Microchip Technology Inc. and its subsidiaries
DS20002188E-page 21
MCP621/1S/2/3/4/5/9
3.1
Analog Outputs
The analog output pins (VOUT) are low-impedance
voltage sources.
3.2
Analog Inputs
The noninverting and inverting inputs (VIN+, VIN–, …)
are high-impedance CMOS inputs with low bias
currents.
3.3
Power Supply Pins
The positive power supply (VDD) is 2.5V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
3.4
Calibration Common Mode
Voltage Input
A low-impedance voltage placed at this input (VCAL)
will set the op amps’ Common mode input voltage
during calibration. If this pin is left open, the Common
mode input voltage during calibration is approximately
VDD/3. The internal resistor divider is disconnected
from the supplies whenever the part is not in
calibration.
3.5
Calibrate/Chip Select Digital Input
This input (CAL/CS, …) is a CMOS, Schmitt-triggered
input that affects the Calibration and Low-Power
modes of operation. When this pin goes high, the part
is placed into a Low-Power mode and the output is
High Z. When this pin goes low, a calibration sequence
is started (which corrects VOS). At the end of the cali-
bration sequence, the output becomes low-impedance
and the part resumes normal operation.
An internal POR triggers a calibration event when the
part is powered-on, or when the supply voltage drops
too low. Thus, the MCP622 parts are calibrated, even
though they do not have a CAL/CS pin.
3.6
Exposed Thermal Pad (EP)
There is an internal connection between the Exposed
Thermal Pad (EP) and the VSS pin; they must be
connected to the same potential on the Printed Circuit
Board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (
JA).



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