MCP621 datasheet(3/68 Pages) MICROCHIP

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DS20002188E-page 3

MCP621/1S/2/3/4/5/9

1.0

ELECTRICAL CHARACTERISTICS

1.1

Absolute Maximum Ratings †

VDD –VSS .......................................................................6.5V

Current at Input Pins ....................................................±2 mA

Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD +1.0V

All Other Inputs and Outputs ......... VSS – 0.3V to VDD +0.3V

Output Short Circuit Current ................................ Continuous

Current at Output and Supply Pins ..........................±150 mA

Storage Temperature ...................................-65°C to +150°C

Max. Junction Temperature ........................................ +150°C

ESD protection on all pins (HBM, MM)

 1 kV, 200V

†Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at those or any other

conditions above those indicated in the operational

listings of this specification is not implied. Exposure to

maximum rating conditions for extended periods may

affect device reliability.

†† See Section 4.2.2, Input Voltage and Current

Limits.

1.2

Specifications

TABLE 1-1:

DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,

VCM = VDD/3, VOUT  VDD/2, VL = VDD/2, RL = 2 k to VL and CAL/CS =VSS (refer to Figure 1-2).

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Input Offset

Input Offset Voltage

VOS

-200

—

+200

µV

After calibration (Note 1)

Input Offset Voltage Trim Step

Size

VOSTRM

—37

200

µV

(Note 2)

Input Offset Voltage Drift

VOS/TA

—

±2.0

—

µV/°C TA = -40°C to +125°C

Power Supply Rejection Ratio

PSRR

—

Input Current and Impedance

Input Bias Current

—5

—

Across Temperature

—

100

—

TA =+85°C

Across Temperature

—

1700

5,000

TA = +125°C

Input Offset Current

IOS

—±10

—

Common Mode Input

Impedance

ZCM

—1013||9

—

||pF

Differential Input Impedance

ZDIFF

—1013||2

—

||pF

Common Mode

Common Mode Input Voltage

Range

VCMR

VSS  0.3

—

VDD  1.3

(Note 3)

Common Mode Rejection Ratio

CMRR

—

VDD = 2.5V, VCM = -0.3 to

1.2V

CMRR

—

VDD = 5.5V, VCM = -0.3 to

4.2V

Open-Loop Gain

DC Open-Loop Gain

(large signal)

AOL

117

—

VDD = 2.5V,

VOUT = 0.3V to 2.2V

AOL

126

—

VDD = 5.5V,

VOUT = 0.3V to 5.2V

Note 1: Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is

toggled. Thus, 1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.

2: Increment between adjacent VOS trim points; Figure 2-3 shows how this affects the VOS repeatability.

3: See Figure 2-6 and Figure 2-7 for temperature effects.

4: The ISC specifications are for design guidance only; they are not tested.

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