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MCP621 数据表(PDF) 5 Page - Microchip Technology |
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MCP621 数据表(HTML) 5 Page - Microchip Technology |
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5 / 68 page  2009-2021 Microchip Technology Inc. and its subsidiaries DS20002188E-page 5 MCP621/1S/2/3/4/5/9 TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/ 2, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CAL/CS =VSS (refer to Figure 1-1 and Figure 1-2). Parameters Sym. Min. Typ. Max. Units Conditions CAL/CS Low Specifications CAL/CS Logic Threshold, Low VIL VSS —0.2VDD V CAL/CS Input Current, Low ICSL —0 — nA CAL/CS = 0V CAL/CS High Specifications CAL/CS Logic Threshold, High VIH 0.8VDD VDD V CAL/CS Input Current, High ICSH —0.7 — µA CAL/CS = VDD GND Current ISS -3.5 -1.8 — µA Single, CAL/CS = VDD = 2.5V ISS -8 -4 — µA Single, CAL/CS = VDD = 5.5V ISS -5 -2.5 — µA Dual, CAL/CS = VDD = 2.5V ISS -10 -5 — µA Dual, CAL/CS = VDD = 5.5V CAL/CS Internal Pull-Down Resistor RPD —5 — M Amplifier Output Leakage IO(LEAK) — 50 — nA CAL/CS = VDD, TA = 125°C POR Dynamic Specifications VDD Low to Amplifier Off Time (output goes High Z) tPOFF — 200 — ns G = +1 V/V, VL = VSS, VDD = 2.5V to 0V step to VOUT =0.1 (2.5V) VDD High to Amplifier On Time (including calibration) tPON 100 200 300 ms G = +1 V/V, VL = VSS, VDD = 0V to 2.5V step to VOUT =0.9 (2.5V) CAL/CS Dynamic Specifications CAL/CS Input Hysteresis VHYST — 0.25 — V CAL/CS Setup Time (between CAL/CS edges) tCSU 1— — µs G = +1 V/V, VL = VSS (Notes 2, 3, 4) CAL/CS = 0.8VDD to VOUT = 0.1 (VDD/ 2) CAL/CS High to Amplifier Off Time (output goes High Z) tCOFF — 200 — ns G = +1 V/V, VL = VSS, CAL/CS = 0.8VDD to VOUT = 0.1 (VDD/ 2) CAL/CS Low to Amplifier On Time (including calibration) tCON —3 4 ms G = +1 V/V, VL = VSS, MCP621 and MCP625, CAL/CS = 0.2VDD to VOUT =0.9 (VDD/2) tCON —6 8 ms G = +1 V/V, VL = VSS, MCP629, CAL/CS = 0.2VDD to VOUT =0.9 (VDD/2) Note 1: The MCP622 single, MCP625 dual and MCP629 quad have their CAL/CS inputs internally pulled down to VSS (0V). 2: This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised before the calibration is complete, the calibration will be aborted and the part will return to Low-Power mode. 3: For the MCP625 dual, there is an additional constraint. CALA/CSA and CALB/CSB can be toggled simultaneously (within a time much smaller than tCSU) to make both op amps perform the same function simultaneously. If they are toggled independently, then CALA/CSA (CALB/CSB) cannot be allowed to toggle while op amp B (op amp A) is in Calibration mode; allow more than the maximum tCON time (4 ms) before the other side is toggled. 4: For the MCP629 quad, there is an additional constraint. CALAD/CSAD and CALBC/CSBC can be toggled simultaneously (within a time much smaller than tCSU) to make all four op amps perform the same function simultaneously, and the maximum tCON time is approximately doubled (8 ms). If they are toggled independently, then CALAD/CSAD (CALBC/ CSBC) cannot be allowed to toggle while op amps B and C (op amps A and D) are in Calibration mode; allow more than the maximum tCON time (8 ms) before the other side is toggled. |
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