MCP621 datasheet(24/68 Pages) MICROCHIP

24 / 68 page

MCP621/1S/2/3/4/5/9

DS20002188E-page 24

 2009-2021 Microchip Technology Inc. and its subsidiaries

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the Common

mode voltage (VCM) is below ground (VSS); see

Figure 2-15. Applications that are high-impedance may

need to limit the usable voltage range.

4.2.3

NORMAL OPERATION

The input stage of the MCP621/1S/2/3/4/5/9 op amps

use a differential PMOS input stage. It operates at low

Common mode input voltage (VCM), with VCM up to

VDD – 1.3V and down to VSS – 0.3V. The input offset

voltage (VOS) is measured at VCM =VSS –0.3V and

VDD – 1.3V to ensure proper operation. See Figure 2-6

and Figure 2-7 for temperature effects.

When operating at very low noninverting gains, the out-

put voltage is limited at the top by the VCM range

(< VDD –1.3V); see Figure 4-5.

FIGURE 4-5:

Unity Gain Voltage

Limitations for Linear Operation.

4.3

Rail-to-Rail Output

4.3.1

MAXIMUM OUTPUT VOLTAGE

The Maximum Output Voltage (see Figure 2-16 and

Figure 2-17) describes the output range for a given

load. For instance, the output voltage swings to within

40 mV of the negative rail with a 2 k

 load tied to VDD/

4.3.2

OUTPUT CURRENT

Figure 4-6 shows the possible combinations of output

voltage (VOUT) and output current (IOUT). IOUT is

positive when it flows out of the op amp into the

external circuit.

FIGURE 4-6:

Output Current.

4.3.2.1

Power Dissipation

Since the output short-circuit current (ISC) is specified

at ±70 mA (typical), these op amps are capable of both

delivering

and

dissipating

significant

power.

Two common loads, and their impact on the op amp’s

power dissipation, will be discussed.

Figure 4-7 shows a resistive load (RL) with a DC output

voltage (VOUT). VL is RL’s ground point, VSS is usually

ground (0V) and IOUT is the output current. The input

currents are assumed to be negligible.

FIGURE 4-7:

Diagram for Resistive Load

Power Calculations.

The DC currents are:

EQUATION 4-1:

The DC op amp power is:

EQUATION 4-2:

The maximum op amp power, for resistive loads at DC,

occurs when VOUT is halfway between VDD and VL, or

halfway between VSS and VL:

EQUATION 4-3:

VIN

VDD

VOUT

VSS V



IN V



OUT

VDD 1.3V

–



MCP62X

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

IOUT (mA)

RL = 10Ω

RL = 100Ω

RL = 2 kΩ

VOH Limited

VOL Limited

(VDD = 5.5V)

VDD

VOUT

IDD

ISS

IOUT

VSS

MCP62X

IOUT

VOUT VL

–

--------------------------

IDD IQ max 0 IOUT





ISS

– Q min 0 IOUT





Where:

IQ = Quiescent supply current for one op

amp (mA/amplifier)

VOUT = A DC value (V)

POA

IDD VDD VOUT

–

 I

SS VSS

VOUT

–



max POA



IDD VDD VSS

–



max

2 V

–

VL VSS

–





4RL

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