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M58BW16F 数据表(PDF) 59 Page - STMicroelectronics

部件名 M58BW16F
功能描述  16 or 32 Mbit (x32, Boot Block, Burst) 3.3V supply Flash memories
PDF  81 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M58BW16F 数据表(HTML) 59 Page - STMicroelectronics

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M58BW16F, M58BW32F
DC and AC parameters
59/81
Table 21.
Synchronous Burst Read AC characteristics(1) (2)
Symbol
Parameter
Test Condition
M58BWxxF
Unit
45
55
f
Clock frequency
X-Latency = 3
Max
40
33
MHz
X-Latency = 4
Max
56
40
MHz
X-Latency = 5 or 6
Max
75
56
MHz
tAVKH
Address Valid to Valid Clock Edge,
E = VIL, L = VIL
X-Latency = 3
Min
9
6
ns
E = VIL, L = VIL
X-Latency = 4, 5 or 6
Min
6
6
ns
tKHKL
Clock High Time
Min
6
6
ns
tKLKH
Clock Low Time
Min
6
6
ns
tBHKH
Burst Address Advance High to Valid
Clock Edge
E = VIL, G = VIL, L = VIH
Min
8
8
ns
tBLKH
Burst Address Advance Low to Valid
Clock Edge
E = VIL, G = VIL, L = VIH
Min
8
8
ns
tELKH
Chip Enable Low to Valid Clock Edge
L = VIL
X-Latency = 3
Min
9
6
ns
L = VIL
X-Latency = 4, 5 or 6
Min
6
6
ns
tGLQV
Output Enable Low to Output Valid
E = VIL, L = VIH
Max
15
15
ns
tKHAX
Valid Clock Edge to Address Transition
E = VIL
Min
5
5
ns
tKHEL
Valid Clock Edge to Chip Enable Low
L = VIL
Min
0
0
ns
tKHLL
Valid Clock Edge to Latch Enable Low
E = VIL
Min
0
0
ns
tKHLH
Valid Clock Edge to Latch Enable High
E = VIL
Min
0
0
ns
tKHQX
Valid Clock Edge to Output Transition
E = VIL, G = VIL, L = VIH
Min
2
2
ns
tLLKH
Latch Enable Low to Valid Clock Edge,
E = VIL
X-Latency = 3
Min
9
6
ns
E = VIL
X-Latency = 4, 5 or 6
Min
6
6
ns
tRLKH
Valid Data Ready Low to Valid Clock
Edge
E = VIL, G = VIL, L = VIH
Min
6
6
ns
tKHQV
Valid Clock Edge to Output Valid
E = VIL, G = VIL, L = VIH
Max
8
8
ns
1.
Data output should be read on the valid clock edge.
2.
For other timings see Table 18: Asynchronous Bus Read AC characteristics.



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