M58BW16F datasheet(7/81 Pages) STMICROELECTRONICS

7 / 81 page

M58BW16F, M58BW32F

Description

7/81

Description

The M58BW16F and M58BW32F are 16 and 32 Mbit non-volatile Flash memories,

respectively. They can be erased electrically at block level and programmed in-system on a

Double-Word basis using a 2.7V to 3.6V or 2.5V to 3.3V VDD supply for the circuit and a

2.4V to 3.6V VDDQ supply voltage for the Input and Output buffers.

In the rest of the document the M58BW16F and M58BW32F will be referred to as

M58BWxxF unless otherwise specified.

The devices support Asynchronous (Latch Controlled and Page Read) and Synchronous

Bus operations. The Synchronous Burst Read Interface allows a high data transfer rate

controlled by the Burst Clock signal, K. It is capable of bursting fixed or unlimited lengths of

data. The burst type, latency and length are configurable and can be easily adapted to a

large variety of system clock frequencies and microprocessors. All Write operations are

Asynchronous. On power-up the memory defaults to Read mode with an Asynchronous

Bus.

The device features an asymmetrical block architecture:

●

The M58BW32F has an array of 62 main blocks of 512 Kbits each, plus 4 large

parameter blocks of 128Kbits each and 8 small parameter blocks of 64 Kbits each. The

large and small parameter blocks are located either at the top (M58BW32FT) or at the

bottom (M58BW32FB) of the address space. The first large parameter block is referred

to as Boot Block and can be used either to store a boot code or parameters. The

memory array organization is detailed in Table 2: M58BW32F top boot block addresses

and Table 3: M58BW32F Bottom Boot Block Addresses.

●

The M58BW16F has an array of 8 parameter blocks of 64Kb each and 31 main blocks

of 512Kb each. In the M58BW16FT the parameter blocks are located at the top of the

address space whereas in the M58BW16FB, they are located at the bottom. The

memory array organization is detailed in Table 4: M58BW16F top boot block addresses

and Table 5: M58BW16F bottom boot block addresses.

Program and Erase commands are written to the Command Interface of the memory. An on-

chip Program/Erase Controller simplifies the process of programming or erasing the

memory by taking care of all of the special operations that are required to update the

memory contents. The end of a Program or Erase operation can be detected and any error

conditions identified in the Status Register. The command set required to control the

memory is consistent with JEDEC standards.

Erase can be suspended in order to perform either Read or Program in any other block, and

then resumed. Program can be suspended to Read data in any other block, and then

resumed. Each block can be programmed and erased over 100,000 cycles.

M58BW16F 数据表(PDF) 7 Page - STMicroelectronics

M58BW16F 数据表(HTML) 7 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

数据表下载