M58BW16F datasheet(33/81 Pages) STMICROELECTRONICS

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M58BW16F, M58BW32F

Command interface

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4.4

Read Status Register command

The Read Status Register command is used to read the Status Register. One Bus Write

cycle is required to issue the Read Status Register command. Once the command is issued

subsequent Bus Read operations read the Status Register until another command is issued.

The Status Register information is present on the output data bus (DQ0-DQ7) when Chip

Enable E and Output Enable G are at VIL and Output Disable is at VIH.

An interactive update of the Status Register bits is possible by toggling Output Enable or

Output Disable. It is also possible during a Program or Erase operation, by de-activating the

device with Chip Enable at VIH and then reactivating it with Chip Enable and Output Enable

at VIL and Output Disable at VIH.

The content of the Status Register may also be read at the completion of a Program, Erase

or Suspend operation. During a Block Erase or Program command, DQ7 indicates the

Program/Erase Controller status. It is valid until the operation is completed or suspended.

See the section on the Status Register and Table 13 for details on the definitions of the

Status Register bits.

4.5

Clear Status Register command

The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status

Once the command is issued the memory returns to its previous mode, subsequent Bus

Read operations continue to output the same data.

The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new

Program, Erase, Block Protect or Block Unprotect command is issued. If any error occurs

then it is essential to clear any error bits in the Status Register by issuing the Clear Status

4.6

Block Erase command

The Block Erase command can be used to erase a block. It sets all of the bits in the block to

‘1’. All previous data in the block is lost. If the block is protected then the Erase operation will

abort, the data in the block will not be changed and the Status Register will output the error.

Two Bus Write operations are required to issue the command; the first write cycle sets up

the Block Erase command, the second write cycle confirms the Block erase command and

latches the block address in the Program/Erase Controller and starts the Program/Erase

Controller. The sequence is aborted if the Confirm command is not given and the device will

output the Status Register Data with bits 4 and 5 set to '1'.

Once the command is issued subsequent Bus Read operations read the Status Register.

See the section on the Status Register for details on the definitions of the Status Register

bits. During the Erase operation the memory will only accept the Read Status Register

command and the Program/Erase Suspend command. All other commands will be ignored.

If PEN is at VIH, the operation can be performed. If PEN goes below VIH, the operation

aborts, the PEN Status bit in the Status Register is set to ‘1’ and the command must be re-

issued.

Typical Erase times are given in Table 12. See Appendix A, Figure 26: Block Erase flowchart

and pseudo code, for a suggested flowchart on using the Block Erase command.

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