M58BW16F datasheet(22/81 Pages) STMICROELECTRONICS

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Signal descriptions

M58BW16F, M58BW32F

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2.9

Latch Enable (L)

The Bus Interface can be configured to latch the Address Inputs on the rising edge of Latch

Enable, L, for Asynchronous Latch Enable Controlled Read or Write or Synchronous Burst

Read operations. In Synchronous Burst Read operations the address is latched on the

active edge of the Clock when Latch Enable is Low, VIL. Once latched, the addresses may

change without affecting the address used by the memory. When Latch Enable is Low, VIL,

the latch is transparent. Latch Enable, L, can remain at VIL for Asynchronous Random Read

and Write operations.

2.10

Burst Clock (K)

The Burst Clock, K, is used to synchronize the memory with the external bus during

Synchronous Burst Read operations. Bus signals are latched on the active edge of the

Clock. In Synchronous Burst Read mode the address is latched on the first rising clock edge

when Latch Enable is Low, VIL, or on the rising edge of Latch Enable, whichever occurs first.

During Asynchronous bus operations the Clock is not used.

2.11

Burst Address Advance (B)

The Burst Address Advance, B, controls the advancing of the address by the internal

address counter during Synchronous Burst Read operations.

Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the

X-latency time has expired. If Burst Address Advance is Low, VIL, the internal address

counter advances. If Burst Address Advance is High, VIH, the internal address counter does

not change; the same data remains on the Data Inputs/Outputs and Burst Address Advance

is not sampled until the Y-latency expires.

The Burst Address Advance, B, may be tied to VIL.

2.12

Valid Data Ready (R)

The Valid Data Ready output, R, can be used during Synchronous Burst Read operations to

identify if the memory is ready to output data or not. The Valid Data Ready output can be

configured to be active on the clock edge of the invalid data read cycle or one cycle before.

Valid Data Ready, at VIH, indicates that new data is or will be available. When Valid Data

Ready is Low, VIL, the previous data outputs remain active.

2.13

Write Protect (WP)

The Write Protect, WP, provides protection against program or erase operations. When

Write Protect, WP, is at VIL, the protection status that has been configured in the Block

Protection Configuration Register is activated. Program and erase operations to protected

blocks are disabled. When Write Protect WP is at VIH all the blocks can be programmed or

erased, if no other protection is used.

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