MP3326

– 16-CHANNEL LED DRIVER WITH I2C AND SEPARATED PDIM/ADIM

MP3326 Rev. 1.0

www.MonolithicPower.com

18

1/4/2021

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PWM Dimming Frequency Setting Register

Addr: 0x00

Bits

Bit Name

Access

Default

Description

7:2

RESERVED

R

000000

Reserved.

1:0

FPWM

R/W

01

PWM dimming frequency (fPWM) setting bit.

00: 220Hz

01: 250Hz

10: 280Hz

11: 330Hz

The following conditions must be met to avoid glitches:



Change the FPWM setting only when the EN bit is set 0.



Write the FPWM register, then wait for 10µs before writing

other registers.

Control Register

Addr: 0x01

Bits

Bit Name

Access

Default

Description

7

FLTEN

R/W

0

RFSH/FLT pin fault indicator enable bit.

0: Disabled. The RFSH/FLT pin refreshes the signal output

1: Enabled

6

LATCH

R/W

1

Latch-off fault response enable bit.

0: Disabled. The device enters hiccup mode if a fault condition is

detected

1: Enabled

5:4

S_TH[1:0]

R/W

00

LED short protection threshold setting register.

00: 2V

01: 3V

10: 4V

11: 5V

3:2

SLEW[1:0]

R/W

00

LED current slew rate setting register.

00: No slew rate

01: 5µs

10: 10µs

11: 20µs

1

PS_EN

R/W

0

Phase shift enable bit.

0: Disable the phase shift function

1: Enable the phase shift function. The rising edge of channel x +

1 occurs 40µs after channel x (e.g. x = 1, 2, ..., 15)

0

EN

R/W

0

Enable bit.

0: Disable the IC

1: Enable the IC