MP3326

– 16-CHANNEL LED DRIVER WITH I2C AND SEPARATED PDIM/ADIM

MP3326 Rev. 1.0

www.MonolithicPower.com

19

1/4/2021

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Refresh Frequency Setting and OTP Fault Register

Addr: 0x02

Bits

Bit Name

Access

Default

Description

7:3

RESERVED

R

0

Reserved.

2

FT_OTP

R

0

Over-temperature (OT) fault indication bit.

0: An OT fault has not occurred

1: An OT fault has occurred

1:0

FRFSH[1:0]

R/W

01

Refresh frequency setting register, 2LSB. If FPWM[1:0] = 01, the

PWM dimming frequency is 250Hz. If RFSH[9:0] = 0x000, the

RFSH/FLT pin outputs high If FRFSH[9:0] = 0x001 to 0x3FF,

fREFRESH can be calculated with the following equation:

PWM

REFRESH

127500

f

f

=

(Hz)

FRFSH 250



All numbers in the above equation are decimal-based. The

refresh frequency does not change until the 8MSB are written.

The default fREFRESH value is 300Hz.

Refresh Frequency Setting Register

Addr: 0x03

Bits

Bit Name

Access

Default

Description

7:0

FRFSH[9:2]

R/W

6A

Refresh frequency setting register, 2LSB. If FPWM[1:0] = 01, the

PWM dimming frequency is 250Hz. If RFSH[9:0] = 0x000, the

RFSH/FLT pin outputs high If FRFSH[9:0] = 0x001 to 0x3FF,

fREFRESH can be calculated with the following equation:

PWM

REFRESH

127500

f

f

=

(Hz)

FRFSH 250



All numbers in the above equation are decimal-based. The refresh

frequency does not change until the 8MSB are written. The default

fREFRESH is 300Hz.

Channel Enable Register (Channels 9

–16)

Addr: 0x04

Bit

Bit Name

Access

Default

Description

7

CH16EN

R/W

1

Channel 16 enable bit.

0: Disabled

1: Enabled

6

CH15EN

R/W

1

Channel 15 enable bit.

0: Disabled

1: Enabled

5

CH14EN

R/W

1

Channel 14 enable bit.

0: Disabled

1: Enabled