MP3326

– 16-CHANNEL LED DRIVER WITH I2C AND SEPARATED PDIM/ADIM

MP3326 Rev. 1.0

www.MonolithicPower.com

14

1/4/2021

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For LED open-load and short protection, hiccup

mode or latch-off mode can be selected by the

LATCH bit through the I2C.

If LATCH = 1, the MP3326 is in latch-off mode.

This means that if a fault is triggered, the fault

channel stays off until VIN or EN is turned off and

reset.

If LATCH = 0, the MP3326 is in hiccup mode. In

this mode, the fault channel tries to conduct for

32µs to detect if the fault is cleared in every 1ms.

/FLT is released if fault condition is removed.

VIN Under-Voltage Lockout (UVLO)

If the input voltage drops to the VIN under-

voltage lockout (UVLO) threshold, the IC stops

working and all I2C registers are reset.

LED Open-Load Protection

When an LED open fault occurs, the LEDx (e.g.

x = 1, 2, ..., 16) voltage drops. If the LEDx voltage

drops below the protection threshold (about

100mV) for 4ms, LED open-load protection is

triggered. Once this occurs, the fault channel

turns off, the corresponding open fault bit CHxO

(x = 1, 2, ..., 16) is set, and the /FLT pin is pulled

low. The fault bit is reset when it is read, and the

/FLT pin is pulled high.

LED Short Protection

If an LED short condition occurs, the VIN -

VLEDx voltage drops. If the VLEDx (e.g. x = 1,

2, ..., 16) voltage exceeds the voltage set by STH

for 4ms, LED short protection is triggered. Once

this occurs, the short channel turns off, the

corresponding CHxS fault bit is set, and /FLT

pulls low.

The LED short protection threshold is configured

by STH 1:0, and can be set to the following

values:

 STH1:0 = 00, 2V

 STH1:0 = 01, 3V

 STH1:0 = 10, 4V

 STH1:0 = 11, 5V

The fault bit is reset when it is read, and the /FLT

pin is pulled high.

Over-Temperature Protection (OTP)

When the IC temperature exceeds 170°C, over-

temperature protection (OTP) is triggered. All

channels turn off, the /FLT pin is pulled low, and

the FT_OTP bit is set. If the temperature drops

by 20°C, the IC recovers, all channels turn on,

and the part resumes normal operation.

I2C INTERFACE REGISTER DESCRIPTION

I2C Chip Address

The device address is 0x30~0x39, and is

configured by the ADDR resistor. The internal

current source flows to the ADDR resistor, then

the voltage of ADDR determines the I2C address.

10 different addresses can be configured

through the ADDR resistor. Table 2 shows how

the I2C address resistor relates to the ISET

resistor.

Table 2: I2C Address Setting

RADDR / RISET

I2C Address

(A3, A2, A1, A0)

<0.05

0000

>0.05, <0.15

0001

>0.15, <0.25

0010

>0.25, <0.35

0011

>0.35, <0.45

0100

>0.45, <0.55

0101

>0.55, <0.65

0110

>0.65, <0.75

0111

>0.75, <0.85

1000

>0.85, <0.95

1001

At start-up, the IC checks the I2C address first;

this address remains the same during operation

unless the IC power is reset.

After the start condition, the I2C-compatible

master sends a 7-bit address followed by an 8th

read (1) or write (0) bit. The 8th bit indicates the

register address to/from which the data will be

written/read.

0

A0

1

1

A3

A1

R/W

A2

Figure 6: The I2C-Compatible Device Address

To avoid a glitch during operation, ensure that

the following conditions are met:

 Change the FPWM1:0 value only when the

EN bit is set 0.

 Write the FPWM register and wait for a 10µs

delay before writing other registers.