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ST7L15 数据表(PDF) 53 Page - STMicroelectronics |
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ST7L15 数据表(HTML) 53 Page - STMicroelectronics |
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53 / 138 page ![]() ST7L15, ST7L19 53/138 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) Figure 33. Dual Timer Mode (ENCNTR2 = 1) PWM0 PWM1 PWM2 PWM3 Dead Time Generator PWM3 Duty Cycle Generator 12-bit Input Capture 12-bit Autoreload Register 2 12-bit Upcounter 2 PWM2 Duty Cycle Generator PWM1 Duty Cycle Generator PWM0 Duty Cycle Generator 12-bit Autoreload Register 1 12-bit Upcounter 1 Output Compare CMP Interrupt OVF1 interrupt OVF2 interrupt Edge Detection Circuit OE0 OE1 OE2 OE3 ATIC DTE bit BPEN bit LTIC OP_EN bit Clock Control One Pulse mode Output Compare CMP Interrupt fCPU Lite Timer 1ms from OFF 1 |
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