ST7L15 datasheet(37/138 Pages) STMICROELECTRONICS

37 / 138 page

ST7L15, ST7L19

37/138

POWER SAVING MODES (cont’d)

9.4 HALT MODE

The HALT mode is the lowest power consumption

mode of the MCU. It is entered by executing the

‘HALT’ instruction when ACTIVE HALT is disabled

(see section 9.5 on page 38 for more details) and

when the AWUEN bit in the AWUCSR register is

cleared.

The MCU can exit HALT mode on reception of ei-

ther a specific interrupt (see Table 5, “Interrupt

Mapping,” on page 32) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt,

the oscillator is immediately turned on and the 256

or 4096 CPU cycle delay is used to stabilize the

oscillator. After the start-up delay, the CPU

resumes operation by servicing the interrupt or by

fetching the reset vector which woke it up (see Fig-

ure 23).

When entering HALT mode, the I bit in the CC reg-

ister is forced to 0 to enable interrupts. Therefore,

if an interrupt is pending, the MCU wakes up im-

mediately.

In HALT mode, the main oscillator is turned off,

stopping all internal processing, including the op-

eration of the on-chip peripherals. All peripherals

are not clocked except those which receive their

clock supply from another clock generator (such

as an external or auxiliary oscillator).

The compatibility of Watchdog operation with

HALT mode is configured by the “WDGHALT” op-

tion bit of the option byte. The HALT instruction,

when executed while the Watchdog system is en-

abled, can generate a Watchdog RESET (see sec-

tion 15.1 on page 126 for more details).

Figure 22. HALT Timing Overview

Figure 23. HALT Mode Flowchart

Notes:

1. WDGHALT is an option bit. See option byte section for

more details.

2. Peripheral clocked with an external clock source can

still be active.

3. Only some specific interrupts can exit the MCU from

HALT mode (such as external interrupt). Refer to Table 5,

“Interrupt Mapping,” on page 32 for more details.

4. Before servicing an interrupt, the CC register is pushed

on the stack. The I bit of the CC register is set during the

interrupt routine and cleared when the CC register is

popped.

5. If the PLL is enabled by option byte, it outputs the clock

after a delay of tSTARTUP (see Figure 11 on page 22).

HALT

RUN

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

[Active Halt disabled]

RESET

INTERRUPT3)

CPU

OSCILLATOR

PERIPHERALS2)

IBIT

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

IBIT

OFF

X4)

CPU

OSCILLATOR

PERIPHERALS

IBIT

X4)

256 OR 4096 CPU CLOCK

DELAY5)

WATCHDOG

ENABLE

DISABLE

WDGHALT1)

WATCHDOG

RESET

CYCLE

HALT INSTRUCTION

(Active Halt disabled)

(AWUCSR.AWUEN=0)

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