ST7L15 datasheet(64/138 Pages) STMICROELECTRONICS

64 / 138 page

ST7L15, ST7L19

64/138

DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d)

11.2.3.7 Force Update (available only on Flash

devices)

In order not to wait for the counterx overflow to

load the value into active DCRx registers, a pro-

grammable counterx overflow is provided. For

both counters, a separate bit is provided which

when set, starts the counters with the overflow val-

ue, that is FFFh. After overflow, the counters start

counting from their respective autoreload register

values.

These bits are FORCE1 and FORCE2 in the

ATCSR2 register. FORCE1 is used to force an

overflow on Counter 1 and FORCE2 is used for

Counter 2. These bits are set by software and re-

set by hardware after the respective counter over-

flow event has occurred.

This feature can be used at any time. All related

features such as PWM generation, Output Com-

pare, Input Capture and One Pulse can be used

this way.

Figure 47. Force Overflow Timing Diagram

11.2.4 Low Power Modes

11.2.5 Interrupts

Note: The CMP and AT4 IC events are connected

to the same interrupt vector. The OVF event is

mapped on a separate vector (see Interrupts chap-

ter). They generate an interrupt if the enable bit is

set in the ATCSR register and the interrupt mask

in the CC register is reset (RIM instruction).

FFF

ARRx

E04

E03

fCNTRx

CNTRx

FORCEx

FORCE2

FORCE1

ATCSR2 Register

Mode

Description

WAIT

No effect on AT timer

HALT

AT timer halted

Interrupt

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Exit

from

Active

Halt

Overflow

Event

OVF1

OVFIE1

Yes

AT4 IC

Event

ICF

ICIE

CMP

Event

CMPFx

CMPIE

Overflow

Event2

OVF2

OVFIE2

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