ST7L15 datasheet(25/138 Pages) STMICROELECTRONICS

25 / 138 page

ST7L15, ST7L19

25/138

SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d)

7.5 RESET SEQUENCE MANAGER (RSM)

7.5.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 14:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

Note: A reset can also be triggered following the

detection of an illegal opcode or prebyte code. Re-

fer to section 12.2.1 on page 95 for further details.

These sources act on the RESET pin which is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of three

phases as shown in Figure 13:

■ Active Phase depending on the RESET source

■ 256 or 4096 CPU clock cycle delay (see table

below)

■ RESET vector fetch

Caution: When the ST7 is unprogrammed or fully

erased, the Flash is blank and the RESET vector

is not programmed. For this reason, it is recom-

mended to keep the RESET pin in low state until

programming mode is entered, in order to avoid

unwanted behavior.

The 256 or 4096 CPU clock cycle delay allows the

oscillator to stabilize and ensures that recovery

has taken place from the RESET state. The short-

er or longer clock cycle delay is automatically se-

lected depending on the clock source chosen by

option byte:

The RESET vector fetch phase duration is two

clock cycles.

If the PLL is enabled by option byte, it outputs the

clock after an additional delay of tSTARTUP (see

Figure 11 on page 22).

Figure 13. RESET Sequence Phases

7.5.2 Asynchronous External RESET Pin

The RESET pin is both an input and an open-drain

output with integrated RON weak pull-up resistor.

This pull-up has no fixed value but varies in ac-

cordance with the input voltage. It can be pulled

low by external circuitry to reset the device. See

Section 13 ELECTRICAL CHARACTERISTICS

for more details.

A RESET signal originating from an external

source must have a duration of at least th(RSTL)in in

order to be recognized (see Figure 15). This de-

tection is asynchronous and therefore the MCU

can enter the RESET state even in HALT mode.

Clock Source

CPU Clock

Cycle Delay

Internal RC Oscillator

256

External clock (connected to CLKIN pin)

256

External Crystal/Ceramic Oscillator

(connected to OSC1/OSC2 pins)

4096

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

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