Data Sheet S15535EJ3V0DS

3

µPD720100A

PCI Bus Interface

:handles 32-bits 33 MHz PCI Bus master and target function which comply with PCI

specification release 2.2. The number of enabled ports are set by bit in configuration

space.

Arbiter

:arbitrates among two OHCI Host controller cores and one EHCI Host controller core.

OHCI Host Controller #1

:handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 1, 3, and 5.

OHCI Host Controller #2

:handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4.

EHCI Host Controller

:handles high- (480 Mbps) signaling at port 1, 2, 3, 4, and 5.

Root Hub

:handles USB hub function in Host controller and controls connection (routing)

between Host controller core and port.

PHY

:consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer,

etc

INTA0

:is the PCI interrupt signal for OHCI Host Controller #1.

INTB0

:is the PCI interrupt signal for OHCI Host Controller #2.

INTC0

:is the PCI interrupt signal for EHCI Host Controller.

SMI0

:is the interrupt signal which is specified by Open Host Controller Interface

Specification for USB Rev 1.0a. The SMI signal of each OHCI Host Controller appears

at this signal.

PME0

:is the interrupt signal which is specified by PCI-Bus Power Management Interface

Specification release 1.1. Wakeup signal of each host controller core appears at this

signal.