Data Sheet

ADRF5022

THEORY OF OPERATION

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Rev. 0 | 10 of 12

The ADRF5022 integrates a driver to perform logic function inter-

nally and to provide the advantage of a simplified control interface.

The driver features two digital control input pins (CTRL and EN)

that control the state of RF paths, determining which RF port is in

insertion loss state and which RF port is in isolation state (see Table

7).

POWER SUPPLY

The ADRF5022 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to

minimize RF coupling.

The ideal power-up sequence is as follows:

1. Connect the ground.

2. Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp-up.

3. Power up the digital control inputs. Power the digital control

inputs before the VDD supply can inadvertently forward bias

and damage the internal ESD protection structures. To avoid

this damage, use a series 1 kΩ resistor to limit the current

flowing into the control pin. Use pull-up or pull-down resistors if

the controller output is in a high impedance state after VDD is

powered up and the control pins are not driven to a valid logic

state.

4. Apply an RF input signal.

The ideal power-down sequence is the reverse order of the power-

up sequence.

Single-Supply Operation

The ADRF5022 can operate with a single positive supply voltage

applied to the VDD and VSS pin connected to ground. However,

some performance difference can occur in switching characteristics

and large signal. For more details, see Table 1.

RF INPUT AND OUTPUT

All of the RF ports (RFC, RF1, RF2) are DC-coupled to 0 V, and no

DC blocking is required at the RF ports when the RF line potential

is equal to 0 V.

The RF ports are internally matched to 50 Ω. Therefore, external

matching networks are not required.

When the EN pin is logic low, the logic level applied to the CTRL

pin determines which RF port is in insertion loss state and which

RF port is in isolation state. The insertion loss path conducts the

RF signal between the selected RF throw port and the RF common

port. The isolation path provides high loss between the insertion

loss path and the unselected RF throw port that is terminated to an

internal 50 Ω resistor.

When the EN pin is logic high, the switch is in an all-off state

regardless of the logic state of the CTRL pin. Both the RF1 to RFC

path and the RF2 to RFC path are in an isolation state. The RF1

and RF2 ports are terminated to internal 50 Ω resistors, and the

RFC port becomes reflective open.

The switch design is bidirectional with equal power handling capa-

bilities. The RF input signal can be applied to the RFC port or the

selected RF throw port.

Table 7. Control Voltage Truth Table

Digital Control Inputs

RF Paths

EN

CTRL

RF1 to RFC

RF2 to RFC

Low

Low

Isolation (off)

Insertion loss (on)

Low

High

Insertion loss (on)

Isolation (off)

High

Low

Isolation (off)

Isolation (off)

High

High

Isolation (off)

Isolation (off)