Data Sheet

ADRF5022

APPLICATIONS INFORMATION

analog.com

Rev. 0 | 11 of 12

The ADRF5022 has two power supply pins (VDD and VSS) and

two control pins (CTRL and EN). Figure 18 shows the external

components and connections for supply and control pins. The VDD

and the VSS pin are decoupled with a 100 pF multilayer ceramic

capacitor. The device pinout allows the placement of the decoupling

capacitors close to the device. No other external components are

needed for bias and operation, except DC blocking capacitors on

the RF pins when the RF lines are biased at a voltage different

than 0 V. For more details, see the Pin Configuration and Function

Descriptions section.

Figure 18. Recommended Schematic

RECOMMENDATIONS FOR PCB DESIGN

The RF ports are matched to 50 Ω internally, and the pinout is

designed to mate a coplanar waveguide (CPWG) with a 50 Ω char-

acteristic impedance on the PCB. Figure 19 shows the referenced

CPWG RF trace design for an RF substrate with 8 mil thick Rogers

RO4003 dielectric material. The RF trace with a 14 mil width and

a 7 mil clearance is recommended for 1.5 mil finished copper

thickness.

Figure 19. Example PCB Stack-Up

Figure 20 shows the routing of the RF traces, supply, and control

signals from the device. The ground planes are connected with as

many filled through vias as allowed for optimal RF and thermal

performance. The primary thermal path for the device is the bottom

side.

Figure 20. PCB Routings

Figure 21 shows the recommended layout from the device RF pins

to the 50 Ω CPWG on the referenced stack-up. PCB pads are

drawn 1:1 to device pads. The ground pads are drawn solder mask

defined, and the signal pads are drawn as pad defined. The RF

trace from the PCB pad is extended with the same width until the

package edge and tapered to the RF trace with a 45° angle. The

paste mask is also designed to match the pad without any aperture

reduction and is divided into multiple openings for the paddle.

Figure 21. Recommended RF Pin Transitions

For alternate PCB stack-ups with different dielectric thickness and

CPWG design and for further recommendations, contact Technical

Support .