AD9549 datasheet(39/78 Pages) AD

39 / 78 page

Preliminary Technical Data

AD9549

Rev. PrA | Page 39 of 78

Holdover Sampler and Averager

If activated via the I/O Register Map, the HSA continuously

monitors the data generated by the digital loop filter in the

background. It should be noted that the loop filter data is a

time sequence of frequency adjustments (∆f) to the DDS. The

output of the HSA is routed to a read-only register in the I/O

The first of these destinations (the read-only register) serves as

a "trace buffer" that may be read by the user and the data

processed externally. The second destination (the holdover

control logic) uses the output of the HSA to "peg" the DDS at a

specific frequency upon entry into the holdover state. Hence,

the DDS will assume a frequency specified by the last value

generated by the HSA just prior to entering the holdover state.

The state of the output MUX is established by programming the

I/O Register Map. The default state is such that the ∆f values

pass through the HSA unaltered. In this mode, the output

sample rate is fS/P, the same as the sample rate of the digital loop

filter.

NOTE: P is the divide ratio of the "P"-divider (see “Digital

Loop Filter” on Page 24) and fS is the DAC sample rate.

Alternatively, the MUX can be set to select the averaging path.

In this mode, a "block average" is performed on a sequence of

samples. The length of the sequence is determined by

programming the value of Y (a 4-bit number stored in the I/O

the output sample rate is given by fS/ (P∙2Y+1).

When the number of ∆f samples specified by Y has been

collected, the averaged result is delivered to a 2-stage pipeline.

The last stage of the pipeline contains the value that will be

delivered to the holdover control logic when a transition into

the holdover state occurs. The pipeline is a guarantee that the

averaged ∆f value delivered to the holdover control logic has not

been interrupted by the transition into the holdover state.

The pipeline provides an inherent delay of ∆t = P∙2Y+1/fS.

Hence, the DDS "hold" frequency is the average as it appeared

∆t to 2∆t seconds prior to entering the holdover state. Note that

the user has some control over the duration of ∆t because it is

dependent on the programmed value of Y.

OUTPUT FREQUENCY RANGE CONTROL

Under normal operating conditions, its output frequency is

dynamically changing in response to the output of the digital

loop filter. The loop filter can steer the DDS to any frequency

between DC and fS/2 (with 48-bit resolution). However, the

user is given the option of placing limits on the tuning range of

the DDS via two 48-bit registers in the I/O Register Map: FTW

Upper Limit and FTW Lower Limit. If the tuning word input

exceeds the upper or lower frequency limit boundaries, the

tuning word is clipped to the appropriate value. The default

setting for these registers is fS/2 and DC, respectively.

It may be desirable to limit the output range of the DDS to a

narrow band of frequencies (for example, to achieve better jitter

performance in conjunction with a band pass filter). See “Use of

Narrowband Filter for High Performance” on Page 40 for more

information about this feature.

Loop

Filter

DDS/DAC

Phase

Detector

External

Reconstruction

Filter

REF IN

Frequency

Limiter

Loop

Filter

DDS/DAC

Phase

Detector

External

Reconstruction

Filter

REF IN

Low Pass

Band Pass

Figure 24: Application of the Frequency Limiter

RECONSTRUCTION FILTER

The origin of the output clock signal produced by the AD9549

is the combined DDS and DAC. The DAC output signal

appears as a sinusoid sampled at fS. The frequency of the

sinusoid is determined by the frequency tuning word (FTW)

that appears at the input to the DDS. The DAC output is

typically passed through an external reconstruction filter that

serves to remove the artifacts of the sampling process and other

spurs outside the filter bandwidth. The signal is then brought

back on-chip to be converted to a square wave that is routed

internally to the output clock driver or the 2x DLL multiplier.

Since the DAC constitutes a sampled system, its output must be

filtered so that the analog waveform accurately represents the

digital samples supplied to the DAC input. The unfiltered DAC

output contains the desired base band signal, which extends

from DC to the Nyquist frequency (fS/2). It also contains

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