AD9549 datasheet(66/78 Pages) AD

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AD9549

Preliminary Technical Data

Rev. PrA | Page 66 of 78

I/O REGISTER DESCRIPTION

Serial Port Configuration (0000 – 0005)

0000; Serial Configuration; bits D4 – D7 are mirror image of D0 – D3

[0] SDO Active: Enables SDO pin 1=SDO pin enabled (four-wire serial port mode.) 0= three-wire mode.

[1] LSB First: Sets bit order for serial port. 1=LSB first. 0=MSB first. IO_UPDATE must occur in order to take effect.

[2] Soft Reset: Resets register map except for register 0000. Setting this bit forces a soft reset, meaning that S1-S4 are not tri-

stated, nor is their state read when this bit is cleared. The 9549 will assume the values of S1-S4 that were present during the last

hard reset. This bit is not self-clearing, and all other registers will be restored to their default values after a soft reset.

[3] Long Instruction: Read-only: this part only supports long instructions.

0001; Reserved

0002 - 0003; Part ID (read-only)

0004; Serial Options

[0] Read Buffer Register: For buffered registers, serial port read-back reads from actual (active) registers instead of the buffer.

1= Reads the buffered values that will take effect during the next IO_UPDATE.

0= Reads values that are currently in effect.

0005; Serial Options; Self Clearing

[0] Register Update: Software access to the “Register Update” pin function.

Writing a “1” to this bit is identical to performing an IO_UPDATE.

Power Down and Reset

0010; Power Down and Enables; Power up default is defined by start-up pins.

[0] Digital PD; Remove clock from most of digital section; leave serial port usable.

In contrast to Full PD, setting this bit does not de-bias inputs, allowing for quick wake-up.

[1] Full PD; Setting this bit is identical to activating the PD pin, and puts all blocks (except serial port) into power down mode.

Sysclk is turned off.

[2] PD RefB; Power down reference clock B input (and related circuits)

[3] PD RefA; Power down reference clock A input (and related circuits)

[4] PD System Clock PLL: System clock multiplier is powered down. 1= System Clock Multiplier powered down.

[5] Enable Output Doubler; Power up output clock generator doubler. Output Doubler must still be enabled in Register 0200.

[6] Enable CMOS Driver: Power up CMOS output driver. 1= CMOS Driver on.

[7] PD HSTL Driver: Power down HSTL output driver. 1 = HSTL Driver powered down.

0011; Reserved

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