AD9549 datasheet(19/78 Pages) AD

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Preliminary Technical Data

AD9549

Rev. PrA | Page 19 of 78

Diff

Input

REFA_IN

Frequency/Phase Reference A Input. This internally biased input is typically AC-coupled,

and when configured as such, can accept any differential signal.

Diff

Input

REFA_INB

Complementary Frequency/Phase Reference A Input: Complementary signal to the

input provided on pin 12

14, 37, 46,

47, 49

Power

AVDD3

Analog Supply: Connect to a nominal 3.3V supply

REFB_IN

Frequency/Phase Reference B Input. This internally biased input is typically AC-coupled,

and when configured as such, can accept any differential signal whose single-ended

swing is between 0.4 and 3.3V.

REFB_INB

Complementary Frequency/Phase Reference B Input: Complementary signal to the input

provided on pin 15

17, 18

N/C

No Connects: These are excess, unused pins that may be left floating

20, 21

PFD_VRB,

PFD_VRT

These pins must be capacitively decoupled. See the Phase Detector Pin Connections

section for details.

I set

Res

PFD_RSET

Connect a 5k

Ω resistor from this pin to Ground

(see the Phase Detector Pin Connections section).

SYSCLK

System Clock Input

SYSCLKB

Complementary System Clock: Complementary signal to the input provided on pin 27

LOOP_FILTER

System Clock Multiplier Loop Filter: When using the frequency multiplier to drive the

System Clock, an external loop filter must be constructed and attached to this pin.

1.8V

CMOS

CLKMODESEL

Clock Mode Select. Set to GND when using a crystal. Pull up to 1.8V when using either an

oscillator or external clock source. (See the SysClk Inputs section for details on the use of

this pin).

33, 39, 43,

GND

AVSS

Analog Ground: Connect to Ground. NOTE: Pin 43 is a ground shield connection.

1.8V

HSTL

OUTB

Complementary HSTL Output: See spec table and the OUTPUT DRIVERS AND

MULTIPLIER section, under sub heading Primary (Differential) Driver, for details

1.8V

HSTL

OUT

HSTL Output: See specification table and the CLOCK DRIVERS section

3.3V

CMOS

OUT_CMOS

CMOS Output: See specification table and the CLOCK DRIVERS section

FDBK_INB

Complementary Feedback input: In standard operating mode, this pin is connected to

the filtered IOUTB output . This internally biased input is typically AC-coupled, and when

configured as such, can accept any differential signal.

FDBK_IN

Feedback Input: In standard operating mode, this pin is connected to the filtered IOUT

output

DAC_RSET

DAC output current setting resistor. Connect a resistor from this pin to GND . See the

“DAC Output” section.

IOUT

DAC output: Output signal should be filtered and sent back on chip through FDBK_INB

input

IOUTB

Complimentary DAC output: Output signal should be filtered and sent back on chip

through FDBK_IN input

I/O

3.3V

CMOS

REFSELECT

Reference Select input: In manual mode, the REFSELECT pin operates as a high

impedance input pin, while in automatic mode, it operates as a low impedance output

pin. Logic 0 (low) indicates/selects RefA. Logic 1 (high) indicates/selects RefB.

I/O

3.3V

CMOS

HOLDOVER

Holdover: (Active high) In manual holdover mode, this pin is used to force the AD9549

into holdover mode. In automatic holdover mode, it indicates holdover status.

3.3V

CMOS

PWRDOWN

Power Down: When this active high pin is asserted, the device becomes inactive and

enters a low power state.

3.3V

CMOS

RESET

Chip Reset: When this active high pin is asserted, the chip goes into reset. Note: upon

power up, a 10 us reset pulse is automatically generated when the power supplies reach

a threshold and stabilize.

3.3V

IO_UPDATE

I/O Update: A logic transition from 0 to 1 on this pin transfers data from the I/O port

AD9549 数据表(PDF) 19 Page - Analog Devices

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AD9549 数据表(PDF) 19 Page - Analog Devices

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