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ST7538Q 数据表(PDF) 27 Page - STMicroelectronics

部件名 ST7538Q
功能描述  FSK power line transceiver
PDF  44 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7538Q 数据表(HTML) 27 Page - STMicroelectronics

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ST7538Q
Functional description
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5.8.1
Automatic Level Control (ALC)
The Automatic Level Control Block (ALC) is a variable gain amplifier (with 32 non linear
discrete steps) controlled by two analog feed backs acting at the same time. The ALC gain
range is 0dB to 30 dB and the gain change is clocked at 5KHz. Each step increases or
reduces the voltage of 1dB (Typ).
Two are the control loops acting to define the ALC gain:
The Voltage control loop acts to keep the Peak-to-Peak Voltage constant on Vsense.
The gain adjustment is related to the result of a peak detection between the Voltage
waveform on Vsense and two internal Voltage references. It is possible to protect the
Voltage Control Loop against noise by freezing the output level (see Section 6.6:
Output voltage level freeze on page 38).
If Vsense < VCLTH - VCLHYST
The next gain level is increased by 1 step
If VCLTH - VCLHYST < Vsense < VCLTH + VCLHYST
No Gain Change
If Vsense > VCLTH + VLCHYST
The next gain level is decreased by 1 step
The Current control loop acts to limit the maximum Peak Output current inside
ATOP1 and ATOP2.
The current control loop acts through the voltage control loop decreasing the Output
Peak-to-Peak Amplitude to reduce the Current inside the Power Line Interface.
The current sensing is done by mirroring the current in the High side MOS of the Power
Amplifier (not dissipating current Sensing). The Output Current Limit (up to
400mApeak), is set by means of an external resistor (RCL) connected between CL and
PAVss. The resistor converts the current sensed into a voltage signal. The Peak current
sensing block works as the Output Voltage sensing Block:
If V(CL) < CCLTH - CCLHYST
Voltage Control Loop Acting
If CCLTH - CCLHYST < V(CL) < CCLTH + CCLHYST
No Gain Change
If V(CL) > CCLTH + CLCHYST
The next gain level is decreased by 1 step
Figure 14 shows the typical connection of Current an Voltage control loops.
Figure 14. Voltage and current feedback external interconnection example
R1
ALC
VOLTAGE
LOOP
CURRENT
LOOP
Vsense
CL
ATOP/ATO
VRPK
VCLHYST
VCLTH
1.865V (Typ)
CCLHYST
CCLTH
AVss
5.6nF
R2
RCL
80 pF
Vout
D03IN1421



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