ISP1122ABD datasheet(33/48 Pages) PHILIPS

33 / 48 page

Philips Semiconductors

ISP1122A

USB stand-alone hub

Preliminary speciﬁcation

Rev. 01 — 27 March 2000

33 of 48

9397 750 06986

[1]

Operating modes 0, 1, 4 and 5; see Table 4.

[1]

Test circuit: see Figure 22.

[2]

Excluding the ﬁrst transition from Idle state.

[3]

Characterized only, not tested. Limits guaranteed by design.

Table 31: Dynamic characteristics: overcurrent sense pins

VCC = 4.0 to 5.5 V; VGND =0V; Tamb = −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

ttrip

overcurrent trip response time

from OCn LOW to PSWn HIGH

see Figure 14

[1]

--15

Table 32: Dynamic characteristics: analog I/O pins (D

+, D−); full-speed mode [1]

VCC = 4.0 to 5.5 V; VGND =0V; Tamb = −40 to +85 °C; CL = 50 pF; RPU = 1.5 kΩ on D+ to VTERM.; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

tFR

rise time

CL =50pF;

10 to 90% of

|VOH − VOL|

tFF

fall time

CL =50pF;

10 to 90% of

|VOH − VOL|

FRFM

differential rise/fall time

matching (tFR/tFF)

[2] 90

111.11

VCRS

output signal crossover voltage

[2] [3] 1.3

2.0

Data source timing

tDJ1

source differential jitter for

consecutive transitions

see Figure 15

[2] [3]

−3.5

+3.5

tDJ2

source differential jitter for

paired transitions

see Figure 15

[2] [3]

−4-

+4ns

tFEOPT

source EOP width

see Figure 16

[3] 160

175

tFDEOP

source differential data-to-EOP

transition skew

see Figure 16

[3]

−2-

+5ns

Receiver timing

tJR1

receiver data jitter tolerance for

consecutive transitions

see Figure 17

[3]

−18.5

+18.5

tJR2

receiver data jitter tolerance for

paired transitions

see Figure 17

[3]

−9-

+9ns

tFEOPR

receiver SE0 width

accepted as EOP;

see Figure 16

[3] 82

--ns

tFST

width of SE0 during differential

transition

rejected as EOP;

see Figure 18

[3] --14

Hub timing (downstream ports conﬁgured as full-speed)

tFHDD

hub differential data delay

(without cable)

see Figure 19;

CL =0pF

[3] --44

tFSOP

data bit width distortion after

SOP

see Figure 19

[3]

−5-

+5ns

tFEOPD

hub EOP delay relative to tHDD see Figure 20

[3] 0

tFHESK

hub EOP output width skew

see Figure 20

[3]

−15

+15

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