L6701TR datasheet(7/44 Pages) STMICROELECTRONICS

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L6701

2 Pins description and connection diagrams

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REF_IN

Reference Input for the regulation.

Connect directly or through a resistor to the REF_OUT pin. See Section 10.3 for

details. This pin is used as input for the protections.

REF_OUT

Reference Output.

Connect directly or through a resistor to the REF_IN pin. See Section 10.3 for

details.

21 to 26

VID4

VID0, VID5

Voltage IDentification Pins.

Internally pulled up by 12.5µA to 5V, connect to SGND to program a '0' or leave

floating to program a '1'. They allow programming output voltage as specified in

Table 5, Table 6 and Table 7 according to DAC_SEL status.

FBR

Remote Buffer Non Inverting Input.

Connect to the positive side of the load to perform remote sense.

See Section 16 for proper layout of this connection.

FBG

Remote Buffer Inverting Input.

Connect to the negative side of the load to perform remote sense.

See Section 16 for proper layout of this connection.

29 to 31

ISEN3

ISEN1

LS Current Sense Pins.

These pins are used for current balance phase-to-phase as well as for the

system OCP. Connect through a resistor RISEN to the relative PHASEx pin. See

Section 9 and Section 13.6 for details.

CS+

Droop Current Sense non-inverting input.

Connect through RPH-CPH network to the main inductors. Directly connect to

output voltage when Droop function is not required. See Section 10.1 and

Section 10.2 for details.

CS-

Droop Current Sense inverting input.

Connect through resistor RD to the main inductors common node. Leave floating

when Droop Function is not required. See Section 10.1 and Section 10.2 for

details.

This pin also monitors the output for any feedback disconnection. See

Section 13.4 for details.

VSEN

Remote Buffer Output. It manages OVP and UVP protections and PGOOD

(when applicable). See Section 13 for details.

Error Amplifier Inverting Input. Connect with a resistor RFB vs. VSEN and with an

RF - CF toward COMP.

COMP

Error Amplifier Output. Connect with an RF - CF vs. FB.

The device cannot be disabled by pulling down this pin.

PAD

THERMAL

PAD

Thermal pad connects the Silicon substrate and makes good thermal contact

with the PCB to dissipate the power necessary to drive the external MOSFETs.

Connect to the PGND plane with several VIAs to improve thermal conductivity.

Table 1.

Pins description (continued)

Pin n

Name

Function

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