15 System Control Loop Compensation

L6701

36/44

●

is the PWM transfer function where

amplitude and has a typical value of 3V.

Removing the dependence from the Error Amplifier gain, so assuming this gain high enough,

and with further simplifications, the control loop gain results:

The system Control Loop gain (See Figure 18) is designed in order to obtain a high DC gain to

minimize static error and to cross the 0dB axes with a constant -20dB/dec slope with the

desired crossover frequency

zero and two poles; both the poles are fixed once the output filter is designed (LC filter

resonance

Figure 18. Equivalent Control Loop Block Diagram (left) and Bode Diagram (right).

implementation. A zero at

integrator minimizes the static error while placing the zero

resonance assures a simple -20dB/dec shape of the gain.

In fact, considering the usual value for the output filter, the LC resonance results to be at

frequency lower than the above reported zero.

Compensation network can be simply designed placing

frequency

PWM

4

5

---

V

IN

∆V

OSC

-------------------

⋅

=

G

LOOP

s

()

4

5

---

V

IN

∆V

OSC

----------------------

Z

F

s

()

R

FB

---------------

R

O

R

DR OOP

+

R

O

R

L

3

-------

+

--------------------------------------------

1s C

O

R

DROOP

//R

O

ESR

+

()

⋅⋅

+

s

2

C

O

L

3

----

⋅⋅

s

L

O

⋅

------------------

C

O

ESR

⋅

C

O

R

L

3

-------

⋅

++

1

+

⋅

+

-------------------------------------------------------------------------------------------------------------------------------------------

⋅⋅

⋅

⋅

–

=

Reference

FB

COMP

VSEN

FBR

FBG

64k

64k

64k

DROOP

PWM

L / N

ESR

REMOTE BUFFER

dB

ω

K

ω

ω

ESR

ω

T

R

F

R

FB

∆V

OSC

⋅

V

IN

----------------------------------

5

4

---

ω

T

L

3R

DROOP

ESR

+

()

⋅

-------------------------------------------------------

⋅⋅

⋅

=

C

F

C

O

L

3

---

⋅

R

F

--------------------

=