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M700000002 数据表(PDF) 76 Page - SPANSION

部件名 M700000002
功能描述  2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
PDF  128 Pages
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制造商  SPANSION [SPANSION]
网页  http://www.spansion.com
标志 SPANSION - SPANSION

M700000002 数据表(HTML) 76 Page - SPANSION

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74
Am70PDL127BDH/Am70PDL129BDH
November 25, 2003
AD VAN C E
INFORM ATION
pSRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
3. If CE#1ps, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.
4. If CE#1ps, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.
Figure 25.
Pseudo SRAM Write Cycle—WE# Control
Parameter
Symbol
Description
Speed
Unit
66
85
t
WC
Write Cycle Time
Min
70
85
ns
t
WP
Write Pulse Time
Min
50
60
ns
t
CW
Chip Enable to End of Write
Min
60
70
ns
tBW
Data Byte Control to End of Write
Min
60
70
ns
t
AW
Address Valid to End of Write
Min
60
70
ns
tAS
Address Setup Time
Min
0
ns
t
WR
Write Recovery Time
Min
0
ns
tODW
WE# Low to Write to Output High-Z
Max
20
ns
t
OEW
WE# High to Write to Output Active
Min
0
ns
tDS
Data Set-up Time
Min
30
t
DH
Data Hold from Write Time
Min
0
ns
t
CH
CE2 Hold Time
Min
300
µs
t
CEH
Chip Enable High Pulse Width
Min
10
ns
t
WEH
Write Enable High Pulse Width
Min
6
ns
tWC
tWP
tAW
tWEH
tWR
tCW
tBW
Valid Data In
tAS
tCH
tOEW
Addresses
A20 to A0
WE#
CE#1s
CE2s
LB#, UB#
DIN
DQ15 to DQ0
DOUT
DQ15 to DQO
tODW
tDS
tDH
High-Z
(Note 1)
(Note 3)
(Note 4)



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