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PCF85063ATL/1 数据表(PDF) 28 Page - NXP Semiconductors

部件名 PCF85063ATL/1
功能描述  Tiny Real-Time Clock/calendar with alarm function and I2C-bus
PDF  55 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF85063ATL/1 数据表(HTML) 28 Page - NXP Semiconductors

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NXP Semiconductors
PCF85063A
Tiny Real-Time Clock/calendar with alarm function and I2C-bus
When reading the timer, the current countdown value is returned and
not the initial value T. Since it is not
possible to freeze the countdown timer counter during read back, it is recommended to read the register twice
and check for consistent results.
Timer source clock frequency selection of 1 Hz and 1⁄60 Hz is affected by the Offset register. The duration of a
program period varies according to when the offset is initiated. For example, if a 100 s timer is set using the 1
Hz clock as source, then some 100 s periods will contain correction pulses and therefore be longer or shorter
depending on the setting of the Offset register. See Section 7.2.3 to understand the operation of the Offset
register.
7.6.3.1 Countdown timer interrupts
The pulse generator for the countdown timer interrupt uses an internal clock and is dependent on the selected
source clock for the countdown timer and on the countdown value T. As a consequence, the width of the
interrupt pulse varies (see Table 37).
TF and INT become active simultaneously.
INT period (s)
Source clock (Hz)
T = 1[1]
T > 1[1]
4 096
1⁄8 192
1⁄4 096
64
1⁄128
1⁄64
1
1⁄64
1⁄64
1⁄60
1⁄64
1⁄64
Table 37. INT operation
[1]
T = loaded countdown value. Timer stops when T = 0.
8 Characteristics of the I2C-bus interface
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a
Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a
pull-up resistor. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the
HIGH period of the clock pulse, as changes in the data line at this time are interpreted as a control signal (see
Figure 18).
mbc621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Figure 18. Bit transfer
PCF85063A
All information provided in this document is subject to legal disclaimers.
© 2023 NXP B.V. All rights reserved.
Product data sheet
Rev. 7.1 — 8 November 2023
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