PCF5083HSLASH001SLASHF2 datasheet(107/136 Pages) PHILIPS

107 / 136 page

1996 Oct 29

107

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

Table 88 Serial Interface Interrupt Mask Register

Note

1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘

−’ denotes not affected from reset line.

During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other

registers are undefined and have to be set by the controller.

Table 89 IOM®-2 Interface Conﬁguration Register

Note

1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘

−’ denotes not affected from reset line.

During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other

registers are undefined and have to be set by the controller.

BIT

R/W

SYMBOL

OPERATION (if bit is set)

RST = 0

RSTx=0(1)

R/W

IMC_OBE_MASK

Enable the IMC_OBE ﬂag to assert the SI_INT interrupt

condition.

−

R/W

IMC_IBF_MASK

Enable the IMC_IBF ﬂag to assert the SI_INT interrupt

condition.

−

R/W

TXD_OBE_MASK Enable the TXD_OBE ﬂag to assert the SI_INT

interrupt condition.

−

R/W

RXD_IBF_MASK

Enable the RXD_IBF ﬂag to assert the SI_INT interrupt

condition.

−

R/W

EXT_IOM_MASK

Enable the EXT_IOM ﬂag to assert the SI_INT interrupt

condition.

−

BIT

R/W

SYMBOL

OPERATION (if bit is set)

RST = 0

RSTx=0(1)

R/W

IOMEXT_EN

Set to a logic 1 to enable the external IOM®-2 interface

−

R/W

IOMEXT_INV

Set to a logic 1 to invert the external IOM®-2 lines

−

R/W

CLOCK_MODE0

Select the IOM®-2 clock mode

−

R/W

CLOCK_MODE1

−

R/W

CLOCK_MODE2

−

R/W

DATA_MODE

Select the IOM®-2 data mode.

−

R/W

MASTER0_EN

Set to a logic 1 to enable the IOM®-2 master unit 0

−

R/W

MASTER1_EN

Set to a logic 1 to enable the IOM®-2 master unit 1

−

R/W

MASTER0_TS0

Select the IOM®-2 timeslot for the IOM®-2 master unit 0

−

R/W

MASTER0_TS1

−

R/W

MASTER0_TS2

−

R/W

MASTER0_TS3

−

R/W

MASTER1_TS0

Select the IOM®-2 timeslot for the IOM®-2 master unit 1

−

R/W

MASTER1_TS1

−

R/W

MASTER1_TS2

−

R/W

MASTER1_TS3

−

PCF5083H/001/F2 数据表(PDF) 107 Page - NXP Semiconductors

PCF5083H/001/F2 数据表(HTML) 107 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

PCF5083H/001/F2 数据表(PDF) 107 Page - NXP Semiconductors

PCF5083H/001/F2 数据表(HTML) 107 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载