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PCF5083H/001/F2 数据表(PDF) 110 Page - NXP Semiconductors

部件名 PCF5083H/001/F2
功能描述  GSM signal processing IC
PDF  136 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

PCF5083H/001/F2 数据表(HTML) 110 Page - NXP Semiconductors

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1996 Oct 29
110
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
Table 94 Parallel Port Data Register
Note
1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘
−’ denotes not affected from reset line.
During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other
registers are undefined and have to be set by the controller.
Table 95 Parallel Port Data Direction Register
Note
1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘
−’ denotes not affected from reset line.
During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other
registers are undefined and have to be set by the controller.
Table 96 System Configuration Register (SYSCON)
Note
1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘
−’ denotes not affected from reset line.
During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other
registers are undefined and have to be set by the controller.
BIT
R/W
SYMBOL
OPERATION
RST=0
RSTx=0(1)
0 to 5
R/W
PIO0_DATA to PIO5_DATA
PIO0 to PIO5 input or output data
0
BIT
R/W
SYMBOL
OPERATION
RST=0
RSTx=0(1)
0
R
PIO0_DDIR
reserved
0
1 to 5
R/W
PIO1_DDIR to PIO5_DDIR
A logic 1 selects the port as an output.
A logic 0 selects the port as an input.
0
BIT
R/W
SYMBOL
OPERATION (if bit is set)
RST = 0
RSTx=0(1)
0
W
CLK13M
Disable the CLK13M output pin.
0
1
W
CLK20M
Disable the CLK20M output pin.
0
2
W
CLK32K
Disable the CLK32K output pin; PCF5083-2B and
PCF5083-2C only.
0
CLK26M
Disable the CLK26M output pin; PCF5083-3A only.
0
3
W
DSP_CLK0
These two bits select the DSP core input clock.
0
4
W
DSP_CLK1
0
5
W
RS232_CLK
Select the external clock for the RS232 interface
0
6
R
LOCK
When a logic 1, the PLL is out of lock. When a logic 0,
the PLL is in lock.
0



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