PCF5083HSLASH001SLASHF2 datasheet(112/136 Pages) PHILIPS

112 / 136 page

1996 Oct 29

112

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

Table 99 Operations supported by the JTAG-circuitry

Notes

1. For all DSP core specific instructions refer to [1].

2. This instruction is always captured in the state Capture_IR of the TAP controller.

3. This instruction is loaded into the instruction register in the state Reset of the TAP-controller.

INSTRUCTION

BINARY CODE

DESCRIPTION OR VALUE

EXTEST

00000

Refer to IEEE standard

ACUTEST(1)

00001

Test mode for IC production

CONTEST(1)

00010

Test mode for IC production

DCUTEST(1)

00011

Test mode for IC production

IOTEST(1)(1)

00100

Test mode for IC production

FCTTEST(1)

00101

Test mode for IC production

SFTTEST(1)

00110

Test mode for IC production

FCTTESTV(1)

00111

Test mode for IC production

SAMPLE/PRELOAD

01000

Refer to IEEE standard

RESET(1)

10000

Generate a synchronous reset for the DSP core

GO(1)

10001

Restart the DSP core at 0x0000 after the RESET instruction

HIGH-Z

10010

Sets all 3-state pins in their high impedance state; TDI, TDO equal to

BYPASS

CLAMP

10011

Pins like EXTEST. TDI, TDO equal to BYPASS

NMI(1)

10100

Generate a NMI to the DSP core

−

10110

Reserved

−

10111

Reserved

TESTIN(1)

11000

Select the test input register TI

TESTOUT(1)

11001

Select the test output register TO

STATUS

11010

Select the status register

IDCODE(2)

11101

0001 0101110110000110 00000010101 1 (PCF5083-1)

0010 0101110110000110 00000010101 1 (PCF5083-2)

0011 0101110110000110 00000010101 1 (PCF5083-3)

BYPASS(3)

Others

Refer to IEEE standard

PCF5083H/001/F2 数据表(PDF) 112 Page - NXP Semiconductors

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