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AS7343

Register Description

Datasheet

• PUBLIC

DS001046

• v6-00 • 2023-Jun-07

57

│ 27

Addr: 0xFA

CONTROL

Bit

Bit Name

Default

Access

Bit Description

Starts a manual autozero of the spectral engines.

Set SP_EN = 0 before starting a manual autozero for

it to work.

1

FIFO_CLR

0

RW

FIFO Buffer Clear.

Clears all FIFO data, FINT, FIFO_OV, and

FIFO_LVL.

0

CLEAR_SAI_ACT

0

RW

Clear Sleep-After-Interrupt Active.

Clears SAI_ACTIVE, ends sleep, and restarts device

operation.

10.2.2

ADC Timing Configuration / Integration Time

The integration time is set using the ATIME (0x81) and ASTEP (0xD4, 0xD5) registers. The integration

time, in milliseconds, is equal to:

Equation 1: Setting the integration time

������������������������ = (������������������������������ + 1) × (������������������������������ + 1) × 2.78 µ������

It is not allowed that both settings

–ATIME and ASTEP – are set to “0”.

The integration time also defines the full-scale ADC value, which is equal to:

Equation 2: ADC full scale value1

������������������������������������������������������������������������ = (������������������������������ + 1) × (������������������������������ + 1)

ATIME Register (Address 0x81)

Figure 26:

ATIME Register

Addr: 0x81

ATIME

Bit

Bit Name

Default

Access

Bit Description

7:0

ATIME

0x00

RW

Integration Time.

Sets the number of integration steps from 1 to 255.

Value

Integration Time

0

ASTEP

n

ASTEP x (n+1)

1 The maximum ADC count is 65535. Any ATIME/ASTEP field setting resulting in higher ADC full-scale values would result in a

full-scale of 65535.