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AS7343

Datasheet

• PUBLIC

DS001046

• v6-00 • 2023-Jun-07

│ 35

10.2.5

Spectral Interrupt Configuration

The spectral interrupt threshold registers provide 16-bit values to be used as the high and low

thresholds for comparison to the 16-bit CH0_DATA values (ADC CH0). If SP_IEN (register 0xF9) is

enabled and CH0_DATA is not between the two thresholds for the number of consecutive

measurements specified in APERS (register 0xBD) an interrupt is set.

SP_TH_L_LSB Register (Address 0x84)

Figure 39:

SP_TH_L_LSB Register

Addr: 0x84

SP_TH_L_LSB

Bit

Bit Name

Default

Access

Bit Description

7:0

SP_TH_L_LSB

0x00

Spectral Low Threshold LSB

This register provides the low byte of the low

interrupt threshold (CH0).

SP_TH_L_MSB Register (Address 0x85)

Figure 40:

SP_TH_L_MSB Register

Addr: 0x85

SP_TH_L_MSB

Bit

Bit Name

Default

Access

Bit Description

7:0

SP_TH_L_MSB

0x00

Spectral Low Threshold MSB

This register provides the high byte of the low

interrupt threshold (CH0).

Both SP_TH_L registers are combined to a 16-bit

threshold. If the value captured by channel 0 is

below the low threshold and the APERS value is

reached, the bit SP_IEN is set and an interrupt is

generated.

There is an 8-bit data latch implemented that stores

the written low byte until the high byte is written.

Both bytes will be applied at the same time to avoid

an invalid threshold.

Note: The LSB register cannot be changed without

writing to the MSB register. It is recommended to

write to SP_TH_L_LSB and SP_TH_L_MSB within

one I²C command.

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