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AS7343 数据表(PDF) 32 Page - OSRAM GmbH |
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AS7343 数据表(HTML) 32 Page - OSRAM GmbH |
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32 / 58 page ![]() Document Feedback AS7343 Register Description Datasheet • PUBLIC DS001046 • v6-00 • 2023-Jun-07 57 │ 31 10.2.3 ADC Configuration The following registers provide configuration for the 6 integrated ADCs (CH0 to CH5). It is possible to adjust the gain and setup the auto zero compensation for the ADCs. CFG1 Register (Address 0xC6) Figure 31: CFG1 Register Addr: 0xC6 CFG1 Bit Bit Name Default Access Bit Description 7:5 Reserved 0 Reserved 4:0 AGAIN 9 RW Spectral Engines Gain Setting. Sets the spectral sensitivity. VALUE GAIN 0 0.5x 1 1x 2 2x 3 4x 4 8x 5 16x 6 32x 7 64x 8 128x 9 256x 10 512x 11 1024x 12 2048x CFG10 Register (Address 0x65) Figure 32: CFG10 Register Addr: 0x65 CFG10 Bit Bit Name Default Access Bit Description 7:3 Reserved Reserved Reserved Reserved |
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