TMD3702VC datasheet(22/57 Pages) OSRAM

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Datasheet, Public

Page 21

[v2-00] 2023-Mar-14

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TMD3702VC − Register Description

AILTL Register (Address 0x84)

Figure 25:

AILTL Register

AILTH Register (Address 0x85)

Figure 26:

AILTH Register

The Clear (C) channel is compared against low-going 16-bit

threshold value set by AILTL and AILTH.

The contents of the AILTH and AILTL registers are combined and

treated as a sixteen bit threshold value. If the value generated

by the C channel is below the AILTL/H threshold and the APERS

value is reached, the AINT bit is asserted. If AIEN is set, then the

INT pin will also assert.

When setting the 16-bit ALS threshold AILTL must be written

first, immediately followed by AILTH. Internally, the lower 8-bits

are buffered until the upper 8-bits are written. As the upper

8-bits are written both the high and low bytes are

simultaneously latched as a 16-bit value.

Addr:0x84

AILTL

Bit

Bit Name

Default

Access

Bit Description

7:0

AILTL

0x00

This register sets the low byte of the LOW ALS threshold.

Addr: 0x85

AILTH

Bit

Bit Name

Default

Access

Bit Description

7:0

AILTH

0x00

This register sets the high byte of the LOW ALS

threshold.

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