Datasheet, Public

Page 29

[v2-00] 2023-Mar-14

Document Feedback

TMD3702VC − Register Description

CFG1 Register (Address 0x90)

Figure 37:

CFG1 Register

Note(s):

1. The IR multiplexer is not synchronized to the ALS/Color measurement sequencer. It is recommended that after the IR_MUX bit is

changed, to either discard the first ALS/color measurement or wait at least two ALS/color integration times before reading the results.

REVID Register (Address 0x91)

Figure 38:

REVID Register

Addr: 0x90

CFG1

Bit

Bit Name

Default

Access

Bit Description

7

Reserved

0

RW

Reserved. Must be set to default value.

6IR_MUX

0

RW

If set high, the IR (proximity) photodiode is switched into

the Green channel’s data converter. GDATAL/H register

will report IR content. Green photodiode is not

connected in this mode (1).

5Reserved

0

RW

Reserved. Must be set to 1. If this bit is 0, the VCSEL

current will be 2x the nominal value.

4:0

AGAIN

9

(01001)

RW

This field sets the gain of the ALS/Color sensor.

Value

ALS Gain

1 (00001)

1x

3 (00011)

4x

5 (00101)

16x

7 (00111)

64x

8 (01000)

128x

9 (01001)

256x

10 (01010)

512x

All other values

Reserved

Addr: 0x91

REVID

Bit

Bit Name

Default

Access

Bit Description

7:3

Reserved

00000

RO

Reserved.

2:0

REV_ID

001

RO

Device revision number.