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TMD3702VC 数据表(PDF) 35 Page - OSRAM GmbH |
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TMD3702VC 数据表(HTML) 35 Page - OSRAM GmbH |
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35 / 57 page ![]() Page 34 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Register Description REVID2 Register (Address 0x9E) Figure 51: REVID2 Register CFG2 Register (Address 0x9F) Figure 52: CFG2 Register SOFTRST Register (Address 0xA0) Figure 53: SOFTRST Register Addr: 0x9E REVID2 Bit Bit Name Default Access Bit Description 7:4 Reserved 0000 RO Reserved. 3:0 REV_ID 0111 RO Device revision number. Addr: 0x9F CFG2 Bit Bit Name Default Access Bit Description 7:0 Reserved 0 RW Reserved. Must be set to default value. Addr: 0xA0 SOFTRST Bit Bit Name Default Access Bit Description 7:1 Reserved 0 RW Reserved. Must be set to default value. 0SOFTRST 0 RW Writing a 1 to this bit will cause all registers to be reset to their default state. This will immediately terminate all device operation and put the device into the sleep state. |
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