TMD3702VC datasheet(23/57 Pages) OSRAM

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[v2-00] 2023-Mar-14

TMD3702VC − Register Description

AIHTL Register (Address 0x86)

Figure 27:

AIHTL Register

AIHTH Register (Address 0x87)

Figure 28:

AIHTH Register

The Clear (C) channel is compared against high-going 16-bit

threshold value set by AIHTL and AIHTH.

The contents of the AIHTH and AIHTL registers are combined

and treated as a sixteen bit threshold value. If the value

generated by the C channel is above the AIHTL/H threshold and

the APERS value is reached, the AINT bit is asserted. If AIEN is

set, then the INT pin will also assert.

When setting the 16-bit ALS threshold AIHTL must be written

first, immediately followed by AIHTH. Internally, the lower 8-bits

are buffered until the upper 8-bits are written. As the upper

8-bits are written both the high and low bytes are

simultaneously latched as a 16-bit value.

Addr: 0x86

AIHTL

Bit

Bit Name

Default

Access

Bit Description

7:0

AIHTL

0x00

This register sets the low byte of the HIGH ALS

threshold.

Addr: 0x87

AIHTH

Bit

Bit Name

Default

Access

Bit Description

7:0

AIHTH

0x00

This register sets the high byte of the HIGH ALS

threshold.

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