IA82527-PLC44A-R datasheet(27/45 Pages) INNOVASIC

27 / 45 page

IA82527

04 May 2007

CAN Serial Communications Controller

As of Production Ver. 00

PRELIMINARY



 2007

EN21070504-00

www.Innovasic.com

Customer Support:

Page 27 of 45

1-888-824-4184

Table 8. Mode 0 and Mode 1 General Bus and ready Timing

Symbol

Parameter

Minimum

Maximum

1/tXTAL

Oscillator Frequency

8 MHz

16 MHz

1/tSCLK

System Clock Frequency

4 MHz

10 MHz

1/tMCLK

Memory Clock Frequency

2 MHz

8 MHz

tAVLL

Address Valid to ale Low

7.5 ns

—

tLLAX

Address Hold after ale Low

10 ns

—

tLHLL

ale High Time

30 ns

—

tLLRL

ale Low to rd_n Low

20 ns

—

tCLLL

cs_n Low to ale Low

10 ns

—

tQVWH

Data Setup to wr_n or wrh_n High

27 ns

—

tWHQX

Input Data Hold after wr_n or wrh_n High

10 ns

—

tWLWH

wr_n or wrh_n Pulse Width

30 ns

—

tWHLH

wr_n or wrh_n High to Next ale High

8 ns

—

tWHCH

wr_n or wrh_n High to cs_n High

0 ns

—

tRLRH

rd_n Pulse Width

This time is long enough to initiate a double read

cycle by loading the High Speed Registers (04H,

05H), but is too short to read from 04H and 05H

(see tRLDV).

40 ns

—

tRLDV

rd_n Low to Data Valid

(Only for Registers 02H, 04H, 05H)

0 ns

55 ns

tRLDV1

rd_n Low Data to Data Valid (for all Registers

except 02H, 04H, 05H)

for Read Cycle without a Previous Write

—

1.5 tMCLK + 100 ns

tRLDV1

rd_n Low Data to Data Valid (for all Registers

except 02H, 04H, 05H)

for Read Cycle with a Previous Write

—

3.5 tMCLK + 100 ns

tRHDZ

Data Float after rd_n High

0 ns

45 ns

cs_n Low to ready Setup

(Load Capacitance on the ready

Output = 50 pF, VOL = 1.0 V)

—

32 ns

tCLYV

cs_n Low to ready Setup

(Load Capacitance on the ready

Output = 50 pF, VOL = 0.45 V)

—

40 ns

tWLYZ

wr_n or wrh_n Low to ready Float for a Write

Cycle if No Previous Write is Pending

—

145 ns

continued

. . .

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