IA82527-PLC44A-R datasheet(34/45 Pages) INNOVASIC

34 / 45 page

IA82527

04 May 2007

CAN Serial Communications Controller

As of Production Ver. 00

PRELIMINARY



 2007

EN21070504-00

www.Innovasic.com

Customer Support:

Page 34 of 45

1-888-824-4184

Table 10. Mode 3 Asynchronous Operation Timing

Symbol

Parameter

Minimum

Maximum

1/tXTAL

Oscillator Frequency

8 MHz

16 MHz

1/tSCLK

System Clock Frequency

4 MHz

10 MHz

1/tMCLK

Memory Clock Frequency

2 MHz

8 MHz

tAVCL

Address or r-w_n Valid to cs_n Low

Setup

3 ns

—

cs_n Low to Data Valid

(for High-Speed Registers 02H, 04H, and

05H)

0 ns

55 ns

cs_n Low to Data Valid

(for Low-Speed Registers)

Read Cycle without Previous Write

0 ns

1.5 tmclk + 100 ns

tCLDV

cs_n Low to Data Valid

(for Low-Speed Registers)

Read Cycle with Previous Write

0 ns

3.5 tmclk + 100 ns

dsack0_n Low to Output Data Valid

(for High-Speed Read Registers)

—

23 ns

tKLDV

dsack0_n Low to Output Data Valid

(for Low-Speed Read Registers)

< 0 ns

—

tCHDV

Input Data Hold after cs_n High

15 ns

—

tCHDH

Output Data Hold after cs_n High

0 ns

—

tCHDZ

cs_n High to Output Data Float

—

35 ns

tCHKH

cs_n High to dsack0_n = 2.4V

(An on-chip pull-up will drive dsack0_n to

approximately 2.4V; an external pull-up is

required to drive this signal to a higher

voltage.)

0 ns

55 ns

tCHKH

cs_n High to dsack0_n = 2.8V

—

150 ns

tCHKZ

cs_n High to dsack0_n Float

0 ns

100 ns

tCHCL

cs_n Width between Successive Cycles

25 ns

—

tCHAI

cs_n High to Address Invalid

7 ns

—

tCLCH

cs_n Width Low

65 ns

—

tDVCH

CPU Write Data Valid to cs_n High

20 ns

—

continued

. . .

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