IA82527-PLC44A-R datasheet(32/45 Pages) INNOVASIC

32 / 45 page

IA82527

04 May 2007

CAN Serial Communications Controller

As of Production Ver. 00

PRELIMINARY



 2007

EN21070504-00

www.Innovasic.com

Customer Support:

Page 32 of 45

1-888-824-4184

Table 9. Mode 2 General Bus Timing

Symbol

Parameter

Minimum

Maximum

1/tXTAL

Oscillator Frequency

8 MHz

16 MHz

1/tSCLK

System Clock Frequency

4 MHz

10 MHz

1/tMCLK

Memory Clock Frequency

2 MHz

8 MHz

tAVSL

Address Valid to as Low

7.5 ns

tSLAX

Address Hold after as Low

10 ns

tELDZ

Data Float after e Low

0 ns

45 ns

e High to Data Valid for Registers 02H,

04H, 05H

0 ns

45 ns

e High to Data Valid (all Registers except

for 02H, 04H, 05H) for Read Cycle without a

Previous Write

—

1.5 tmclk + 100 ns

tEHDV

e High to Data Valid (all Registers except

for 02H, 04H, 05H) for Read Cycle with a

Previous Write

—

3.5 tmclk + 100 ns

tQVEL

Data Setup to e Low

30 ns

—

tELQX

Input Data Hold after e Low

20 ns

—

tELDV

e Low to Output Data Valid on Port 1/2

tmclk

2 tmclk + 500 ns

tEHEL

e High Time

45 ns

tSHSL

as High Time

30 ns

—

tRSEH

Setup Time of r-w_n to e High

30 ns

—

tSLEH

as Low to e High

20 ns

—

tCLSL

cs_n Low to as Low

20 ns

—

tELCH

e Low to cs_n High

0 ns

—

tCOPD

clkout Period

(CDV is the value loaded in the CLKOUT

(CDV + 1)

• t

osc

tCHCL

clkout High Period

(CDV is the value loaded in the CLKOUT

(CDV + 1)

• ½ t

osc – 10

(CDV + 1)

• ½ t

osc – 15

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