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IA82527-PLC44A-R 数据表(PDF) 40 Page - InnovASIC, Inc |
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IA82527-PLC44A-R 数据表(HTML) 40 Page - InnovASIC, Inc |
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40 / 45 page ![]() IA82527 04 May 2007 CAN Serial Communications Controller As of Production Ver. 00 PRELIMINARY Copyright 2007 EN21070504-00 www.Innovasic.com Customer Support: Page 40 of 45 1-888-824-4184 © Table 12. Serial Interface Mode Timing Symbol Parameter Minimum Maximum sclk Serial Port Interface Clock 0.5 MHz 8 MHz tCYC 1/sclk 125 ns 2000 ns tSKHI Minimum Clock High Time 84 ns — tSKLO Minimum Clock Low Time 84 ns — tLEAD Enable Lead Time 70 ns — tLAG Enable Lag Time 109 ns — tACC Access Time — 50 ns tPDO Maximum Data Out Delay Time — 59 ns tHO Minimum Data Out Hold Time 0 ns — tDIS Maximum Data Out Disable Time 665 ns tSETUP Minimum Data Setup Time 35 ns — tHOLD Minimum Data Hold Time 84 ns — tRISE Maximum Time for Input to go from VOL to VOH — 100 ns tFALL Maximum Time for input to go from VOH to VOL — 100 ns tCS Minimum Time between Consecutive cs_n Assertions 670 ns — tCOPD clkout Period (CDV is the value loaded in the CLKOUT Register representing the clkout divisor.) (CDV + 1) * tosc tCHCL clkout High Period (CDV is the value loaded in the CLKOUT Register representing the clkout divisor.) (CDV + 1) * ½ tosc – 10 (CDV + 1) * ½ tosc + 15 |
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