IA82527-PLC44A-R datasheet(10/45 Pages) INNOVASIC

10 / 45 page

IA82527

04 May 2007

CAN Serial Communications Controller

As of Production Ver. 00

PRELIMINARY



 2007

EN21070504-00

www.Innovasic.com

Customer Support:

Page 10 of 45

1-888-824-4184

2.2

Pin/Signal Descriptions

Descriptions of the pin and signal functions for the IA82527 Serial Communications Controller

are provided in Table 3.

Several of the IA82527 pins have different functions depending on the operating mode of the

device. Each of the different signals supported by a pin is listed and defined in Table 3, indexed

alphabetically in the first column of the table. Additionally, the name of the pin associated with

the signal as well as the pin numbers for both the PLCC and QFP packages are provided in the

“Pin” column. If the signal and pin names are the same, no entry is provided in the “Pin-Name”

column.

Table 3. IA82527 Pin/Signal Descriptions

Signal

Name

PLCC

QFP

Description

a0/ad0/icp

a1/ad1/cp

a2/ad2/csas

a3/ad3/ste

a4/ad4/mosi

a5/ad5

a6/ad6/sclk

a7/ad7

address bits 7–0. Input. Mode 3.

When the IA82527 is configured to operate in the 8-bit non-

multiplexed non-Intel

® architecture mode (Mode 3), these lines

provide the 8-bit address bus input to the device.

ad0

a0/ad0/icp

ad1

a1/ad1/cp

ad2

a2/ad2/csas

ad3

a3/ad3/ste

ad4

a4/ad4/mosi

ad5

a5/ad5

ad6

a6/ad6/sclk

ad7

a7/ad7

ad8

ad8/d0/p1.0

ad9

ad9/d1/p1.1

ad10

ad10/d2/p1.2

ad11

ad11/d3/p1.3

ad12

ad12/d4/p1.4

ad13

ad13/d5/p1.5

ad14

ad14/d6/p1.6

ad15

ad15/d7/p1.7

address/data bits 15–0. Input/Output. Mode 1.

When the IA82527 is configured to operate in the 16-bit multiplexed

Intel

® architecture mode (Mode 1), these lines provide the 16-bit

address bus (input) and the 16-bit data bus (input/output) for the

device.

ale

ale/as

address latch enable. Input. Active High. Mode 0 and Mode 1.

When the IA82527 is configured to operate in either the 8-bit

multiplexed Intel

® architecture mode (Mode 0) or the 16-bit

multiplexed Intel

® architecture mode (Mode 1), this signal latches the

address into the device during the address phase of the bus cycle.

continued

. . .

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