Electrical characteristics

VM6101

14/17

Figure 9.

Serial interface timing waveforms

Note:

1

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

2

Unless otherwise specified, all voltages are referenced to ground.

3

Over recommended operating conditions, unless otherwise specified.

4

Table 9.

Serial interface timing (

Note 3)

Symbol

Parameter

Min

Max

Unit

SCL clock frequency

0

100

kHz

SCL clock low period

4.7

µs

SCL clock high period

4.0

µs

(Repeated) START condition setup time

4.7

µs

(Repeated) START condition hold time

4.0

µs

Data setup time

250

ns

Data hold time

300

ns

STOP condition setup time

4.0

ns

Bus free condition between START and STOP conditions

4.7

µs

Rise time of both SDA and SCL signals

300

ns

Fall time of both SDA and SCL signals

300

ns

Capacitive load for each bus line

400

pF

Stop

Start

SCL

SDA

Start

Stop