MPC866PCZP100A datasheet(37/96 Pages) FREESCALE

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MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor

Bus Signal Timing

Figure 23 shows the timing for the asynchronous external master memory access controlled by the GPCM.

Figure 23. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)

Figure 24 shows the timing for the asynchronous external master control signals negation.

Figure 24. Asynchronous External Master—Control Signals Negation Timing

Table 10 shows the interrupt timing for the MPC866/859.

Table 10. Interrupt Timing

Num

Characteristic 1

The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as

level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference

to the CLKOUT.

The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has

no direct relation with the total system interrupt latency that the MPC866/859 is able to support.

All Frequencies

Unit

Min

Max

I39

IRQx valid to CLKOUT rising edge (setup time)

6.00

—

I40

IRQx hold time after CLKOUT

2.00

—

I41

IRQx pulse width low

3.00

—

I42

IRQx pulse width high

3.00

—

I43

IRQx edge-to-edge time

4xTCLOCKOUT

——

CLKOUT

A[0:31],

TSIZ[0:1],

R/W

CSx

B39

B40

B22

CSx, WE[0:3],

OE, GPLx,

BS[0:3]

B43

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