MPC866PCZP100A datasheet(74/96 Pages) FREESCALE

74 / 96 page

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor

FEC Electrical Characteristics

Figure 73 shows signal timings during UTOPIA transmit operations.

Figure 73. UTOPIA Transmit Timing

14 FEC Electrical Characteristics

This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing

specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII

signals use TTL signal levels compatible with devices operating at either 5.0 or 3.3 V.

14.1 MII Receive Signal Timing (MII_RXD [3:0], MII_RX_DV,

MII_RX_ER, MII_RX_CLK)

The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum

frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency – 1%.

Table 33 shows the timings for MII receive signal.

Figure 74 shows the timings for MII receive signal.

Table 33. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup

—

MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold

—

MII_RX_CLK pulse width high

35%

65%

MII_RX_CLK period

MII_RX_CLK pulse width low

35%

65%

MII_RX_CLK period

UtpClk

UTPB

TxEnb

SOC

TxClav

PHSELn

HighZ at MPHY

High-Z at MPHY

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